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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | C8051F221R |
| 寤犲晢锛� | Silicon Laboratories Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 54/146闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC 8051 MCU 8K FLASH 32LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | C8051F2xx |
| 鏍稿績铏曠悊鍣細 | 8051 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 25MHz |
| 閫ｉ€氭€э細 | SPI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 8KB锛�8K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 256 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 22x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 32-LQFP |
| 鍖呰锛� | 鍓垏甯� (CT) |
| 鍏跺畠鍚嶇ū锛� | 336-1009-1 |
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C8051F2xx
Rev. 1.6
15
Figure 1.4. C8051F231 Block Diagram (32 LQFP)
1.1.
CIP-51TM Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F206, C8051F220/1/6 and C8051F230/1/6 utilize Silcon Labs鈥� proprietary CIP-51 microcon-
troller core.
The CIP-51 is fully compatible with the MCS-51TM instruction set.
Standard 803x/805x
assemblers and compilers can be used to develop software. The core contains the peripherals included
with a standard 8052, including three 16-bit counter/timers, a full-duplex UART, 256 bytes of internal RAM,
an optional 1024 bytes of XRAM, 128 byte Special Function Register (SFR) address space, and four byte-
wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes
70% of its instructions in one or two system clock cycles, with only four instructions taking more than four
system clock cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to
execute them is as follows:
Instructions
26
50
5
14
7
3
1
2
1
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Port 0
Latch
Port 1
Latch
JTAG
Logic
TCK
TMS
TDI
TDO
UART
8kbyte
FLASH
256 byte
SRAM
VDD
Monitor,
WDT
SFR Bus
Port 2
Latch
Port 3
Latch
8
0
5
1
C
o
r
e
Timer 0
Timer 1
Timer 2
CP0
CP1
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
P
1
D
r
v
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P
0
D
r
v
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
P
2
D
r
v
CP0+
CP0-
CP1+
CP1-
P
0
M
U
X
Port I/O Mode
& Config.
Port Mux
Control
Comparator
Config.
VDD
GND
Reset
/RST
XTAL1
XTAL2
External
Oscillator
Circuit
System Clock
Internal
Oscillator
Clock & Reset
Configuration
Digital Power
Emulation HW
P
1
M
U
X
CP0
CP1
P
2
M
U
X
SPI
NC
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| C8051F220R | IC 8051 MCU 8K FLASH 48TQFP |
| C8051F012R | IC 8051 MCU 32K FLASH 32LQFP |
| C8051F127R | IC 8051 MCU 128K FLASH 64TQFP |
| C8051F011R | IC 8051 MCU 32K FLASH 48TQFP |
| C8051F010R | IC 8051 MCU 32K FLASH 64TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| C8051F226 | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8KB 8ADC 1KRam RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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| C8051F226DK-A | 鍔熻兘鎻忚堪:DEV KIT F220/221/226/230/231/236 RoHS:鍚� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 閬庢檪/鍋滅敘(ch菐n)闆朵欢绶ㄨ櫉 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 椤炲瀷:MCU 閬╃敤浜庣浉闂�(gu膩n)鐢�(ch菐n)鍝�:Freescale MC68HC908LJ/LK锛�80-QFP ZIF 鎻掑彛锛� 鎵€鍚墿鍝�:闈㈡澘銆佺簻绶�銆佽粺浠�銆佹暩(sh霉)鎿�(j霉)琛ㄥ拰鐢ㄦ埗鎵嬪唺 鍏跺畠鍚嶇ū:520-1035 |
| C8051F226DK-B | 鍔熻兘鎻忚堪:DEV KIT F220/221/226/230/231/236 RoHS:鍚� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 閬庢檪/鍋滅敘(ch菐n)闆朵欢绶ㄨ櫉 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 椤炲瀷:MCU 閬╃敤浜庣浉闂�(gu膩n)鐢�(ch菐n)鍝�:Freescale MC68HC908LJ/LK锛�80-QFP ZIF 鎻掑彛锛� 鎵€鍚墿鍝�:闈㈡澘銆佺簻绶�銆佽粺浠�銆佹暩(sh霉)鎿�(j霉)琛ㄥ拰鐢ㄦ埗鎵嬪唺 鍏跺畠鍚嶇ū:520-1035 |
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