參數(shù)資料
型號(hào): C8051F221R
廠商: Silicon Laboratories Inc
文件頁數(shù): 142/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 32LQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 22x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-LQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1009-1
C8051F2xx
Rev. 1.6
95
SFR Definition 12.2. RSTSRC: Reset Source
(Note: Do not use read-modify-write operations on this register.)
Bit7:
RESERVED.
Bit6:
Not Used. Read only 0b.
Bit5:
C0RSEF: Comparator 0 Reset Enable and Flag
Write
0: Comparator 0 is not a reset source
1: Comparator 0 is a reset source (active low)
Read
Note: The value read from C0RSEF is not defined if Comparator 0 has not been enabled as
a reset source.
0: Source of prior reset was not from Comparator 0
1: Source of prior reset was from Comparator 0
Bit4:
SWRSF: Software Reset Force and Flag
Write
0: No Effect
1: Forces an internal reset. RST pin is not affected.
Read
0: Prior reset source was not from write to the SWRSF bit.
1: Prior reset source was from write to the SWRSF bit.
Bit3:
WDTRSF: Watchdog Timer Reset Flag (Read only)
0: Source of prior reset was not from WDT timeout.
1: Source of prior reset was from WDT timeout.
Bit2:
MCDRSF: Missing Clock Detector Flag (Read only)
0: Source of prior reset was not from Missing Clock Detector timeout.
1: Source of prior reset was from Missing Clock Detector timeout.
Bit1:
PORSF: Power-On Reset Force and Flag
Write
0: No effect
1: Forces a Power-On Reset. RST is driven low.
Read
0: Source of prior reset was not from POR.
1: Source of prior reset was from POR.
Bit0:
PINRSF: HW Pin Reset Flag
0: Source of prior reset was not from RST pin.
1: Source of prior reset was from RST pin.
R
R/W
R
R/W
R
Reset Value
-
C0RSEF
SWRSEF WDTRSF MCDRSF
PORSF
PINRSF
xxxxxxxx
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xEF
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