參數(shù)資料
型號: C8051F015-GQ
廠商: Silicon Laboratories Inc
文件頁數(shù): 86/171頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 64TQFP
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 160
系列: C8051F01x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 621 (CN2011-ZH PDF)
其它名稱: 336-1194
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
4.
PINOUT AND PACKAGE DEFINITIONS
Table 4.1. Pin Definitions
Pin Numbers
Name
F000
F005
F010
F015
F001
F006
F011
F016
F002
F007
F012
F017
Type
Description
VDD
31,
40,
62
23,
32
18,
20
Digital Voltage Supply.
DGND
30,
41,
61
22,
33,
27,
19
17,
21
Digital Ground.
AV+
16,
17
13,
43
9,
29
Positive Analog Voltage Supply.
AGND
5,
15
44,
12
8,
30
Analog Ground.
TCK
22
18
14
D In
JTAG Test Clock with internal pull-up.
TMS
21
17
13
D In
JTAG Test-Mode Select with internal pull-up.
TDI
28
20
15
D In
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of
TCK.
TDO
29
21
16
D Out
JTAG Test Data Output with internal pull-up. Data is shifted out on TDO on
the falling edge of TCK. TDO output is a tri-state driver.
XTAL1
18
14
10
A In
Crystal Input. This pin is the return for the internal oscillator circuit for a
crystal or ceramic resonator. For a precision internal clock, connect a crystal
or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external
CMOS clock, this becomes the system clock.
XTAL2
19
15
11
A Out
Crystal Output. This pin is the excitation driver for a crystal or ceramic
resonator.
/RST
20
16
12
D I/O
Chip Reset. Open-drain output of internal Voltage Supply monitor. Is driven
low when VDD is < 2.7V. An external source can force a system reset by
driving this pin low.
VREF
6
3
A I/O
Voltage Reference. When configured as an input, this pin is the voltage
reference for the MCU. Otherwise, the internal reference drives this pin.
CP0+
4
2
A In
Comparator 0 Non-Inverting Input.
CP0-
3
1
A In
Comparator 0 Inverting Input.
CP1+
2
45
A In
Comparator 1 Non-Inverting Input.
CP1-
1
46
A In
Comparator 1 Inverting Input.
DAC0
64
48
32
A Out
Digital to Analog Converter Output 0. The DAC0 voltage output. (See
Section 7 DAC Specification for complete description).
DAC1
63
47
31
A Out
Digital to Analog Converter Output 1. The DAC1 voltage output. (See
Section 7 DAC Specification for complete description).
AIN0
7
4
A In
Analog Mux Channel Input 0. (See ADC Specification for complete
description).
AIN1
8
5
A In
Analog Mux Channel Input 1. (See ADC Specification for complete
description).
AIN2
9
6
A In
Analog Mux Channel Input 2. (See ADC Specification for complete
description).
AIN3
10
7
A In
Analog Mux Channel Input 3. (See ADC Specification for complete
description).
AIN4
11
8
A In
Analog Mux Channel Input 4. (See ADC Specification for complete
description).
AIN5
12
9
A In
Analog Mux Channel Input 5. (See ADC Specification for complete
description).
21
Rev. 1.7
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