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MSC7110-01/7112-01
Semiconductor
FEDL7110-03
PIN DESCRIPTION
Symbol
V
EE
DATA IN
V
DD
V
SS
Number
of Pins
1
1
1
1
Type
—
I
—
—
Connected
to
Power source
Description
V
DD
-V
SS
: Supply voltage for internal logic
V
DD
-V
EE
: Supply voltage for VF display tube driving circuit
logic
Input of display data of the shift register
Input from the MSB (positive logic).
Shift clock of the shift register.
Data is shifted at the falling edge of SCLK.
Latch clock input for display data.
When this pin is at a "H" level, the data is not latched to pass
through the latch circuit.
When the pin is at a "L" level, the data when the pin is at the
"H" level is latched.
Internal logic reset input upon power-on.
During reset, the 18-bit internal latch, duty cycle register,
digital register, LED register, and write/read address
register are all reset, and the outputs of SEGA to SEGP(*a),
D1 to D12 (*b), and LED1 to LED5 go off.
Connecting of an external capacitor to the pin allows power-
on reset.
SCLK
1
I
Microcontroller
LOAD
1
I
POR
1
I
—
Schmitt with
pull-up
resistor
using diode
OSC I
OSC O
1
1
I
—
Input for oscillation circuit
When an external resistor and a capacitor are connected,
an oscillation circuit is formed.
C=100pF, R=47k
W
f
OSC
=235kHz±20%
O
SEGA-L
SEGA-P
D1-D12
D1-D16
LED1-LED5
O
Anode side of
VF display tube
Grid side of VF
display tube
LED
Output for driving anode electrodes of VF display tube.
The output is complementary.
Output for driving grid electrodes of VF display tube.
The output is complementary.
LED driving output. The output is complementary.
12
16
12
16
5
O
O
*1
*2
2
*1
*a SEGA to SEGL in case of MSC7110-01
*b D1 to D16 in case of MSC7110-01
*1 In case of MSC7110-01
*2 In case of MSC7112-01