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參數(shù)資料
| 型號： | C711201-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 12-Segment x 16-Digit or 16-Segment x12-Digit Display Controller/Driver |
| 中文描述： | 12段× 16位或16段× 12位數(shù)字顯示控制器/驅(qū)動器 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 203K |
| 代理商： | C711201-01 |
13/18
MSC7110-01/7112-01
Semiconductor
FEDL7110-03
Relation between write address and digit output
Corresponding digit
output
F
D16
E
D15
D
D14
C
D13
B
D12
A
D11
9
D10
8
D9
7
D8
6
D7
5
D6
4
D5
3
D4
2
D3
1
D2
0
D1
Write address count
*1
*1
*1
*1
*1: Ignored in the case of MSC7112-01
Inputting Display Data
LED display
Display data is output to the LED1 to LED5 pins in correspondence with each bit by executing
the L. RLOAD command. Input data uses positive logic. When the data is 1, the LED lights.
When the data is 0, the LED goes off.
VF display (RAM direct display)
Set optional data in the digit register and the duty register, and execute the W.A.C LOAD
command to set the display digit position. Execute the DATA DISPLAY command to write the
b0 to b15 (*1) display data in the RAM. The write address counter is incremented by one. The
write address counter counts sequentially 0, 1, 2,------, 14, 15, 0, 1, ----- regardless of the value of
the digit register.
*1 : b
0
to b
11
display data in the case of MSC7110-01.
Brightness Adjustment
The brightness can be adjusted by using the values of the duty cycle register (D.C.R) and the
digit register (D.R). The value of the duty cycle register changes the pulse width (B) at the D1
to D16 output pins, and the value of the digit register changes the cycle (A).
The table below gives the relation between the value of the duty cycle register and the duty.
When all the values of the duty cycle register are 0 (in the case of 16-digit display), the display
is blank.
Dn
B
A
V
DD
V
EE
A=64
￥
n=64
￥
16=1024
n : Number of display digits
D.C.R
b
2
0
0
0
0
b
3
0
0
0
0
b
1
0
0
1
1
b
0
0
1
0
1
B/A
—
4/1024
8/1024
12/1024
DUTY
b
3
0
0
0
0
b
2
1
1
1
1
b
1
0
0
1
1
b
0
0
1
0
1
B/A
16/1024
20/1024
24/1024
28/1024
DUTY
b
3
1
1
1
1
b
2
0
0
0
0
b
1
0
0
1
1
b
0
0
1
0
1
B/A
32/1024
36/1024
40/1024
44/1024
DUTY
b
3
1
1
1
1
b
2
1
1
1
1
b
1
0
0
1
1
b
0
0
1
0
1
B/A
48/1024
52/1024
56/1024
60/1024
DUTY
D.C.R
D.C.R
D.C.R
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