參數(shù)資料
型號： C3ENPA1-DS
英文描述： 5.0 or 3.3V, 256Kbit (32Kbit x 8) ZEROPOWER® SRAM
中文描述： ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂格A1
文件頁數(shù)： 48/114頁
文件大?。?/td> 1893K
代理商： C3ENPA1-DS
48
CHAPTER 2: SIGNAL DESCRIPTIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
General System Interface Signal
Table 18
provides the signal for the Executive Processor reset power status and I/O clock.
The C-3e NP can be powered up with the XP either running or with the XP in reset mode
similar to the CPs. When the XP remains in reset mode, an external host can be used to
control the initialization of the C-3e NP.
Table 18
General System Interface Signal
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
XPUHOT
Y3
1
LVTTL
I
PD
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low
equals reset and High equals active. During normal operation, this is an
external interrupt.
TOTAL PINS
1
F
n
.
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