
User Manual
C166S V2
Interrupt and Exception Handling
User Manual
5-138
V 1.7, 2001-01
Undefined Opcode Trap:
When the instruction currently being decoded by the CPU
does not contain a valid C166S V2 CPU opcode, the UNDOPC flag is set in register
TFR and the CPU enters the undefined opcode trap routine. The instruction that
causes the undefined opcode trap is executed as a NOP.
Parity Fault Trap:
When a parity error is detected in the system, the PARFLT flag is
set in register TFR and the CPU enters the parity fault trap routine. For the C166S V2
CPU, the parity fault is an asynchronous system event. There is no link between the
fault and the instruction flow itself.
Protection Fault Trap:
Whenever one of the special protected instructions is
executed where the opcode of that instruction is not repeated twice in the second word
of the instruction and the byte following the opcode is not the complement of the
opcode, the PRTFLT flag in register TFR is set and the CPU enters the protection fault
trap routine. The protected instructions include DISWDT, EINIT, IDLE, PWRDN,
SRST, ENWDT and SRVWDT. The instruction that causes the protection fault trap is
executed like a NOP.
Illegal Word Operand Access Trap:
Whenever a word operand read or write access
is attempted to an odd byte address, the ILLOPA flag in register TFR is set and the
CPU enters the illegal word operand access trap routine.
5.4
Peripheral Event Controller
The Peripheral Event Controller (PEC) makes a decision about the CPU action required
to manage an interrupt request. It may be either normal interrupt service or fast data
transfer between two memory locations. The C166S V2 PEC controls eight fast data
transfer channels.
If normal interrupt is requested, the CPU temporarily suspends the current program
execution and branches to an interrupt service routine. The current program status and
context must be preserved.
If a PEC channel is selected for servicing an interrupt request, a single word or byte data
transfer between any two memory locations is to be performed. During a PEC transfer,
the normal program execution of the CPU is halted. No internal program status
information needs to be saved. The PEC transfer is the fastest possible interrupt
response. In many cases, a PEC transfer is sufficient to service the peripheral request
(serial channels, for example).
The PEC channels can perform the following actions:
Byte or word transfer
Continuous data transfer
PEC channel-specific interrupt request upon data transfer completion or common for
all channels
“
End of PEC
”
interrupt for enhanced handling
Automatic increment of source or/and destination pointers with support of memory to
memory transfer
Note: PEC transfer is executed if its priority level is higher than current CPU priority level.