
User Manual
C166S V2
Interrupt and Exception Handling
User Manual
5-133
V 1.7, 2001-01
The TRAP instruction has an effect similar to an interrupt request at the same vector.
PSW, CSP (in segmentation mode), and IP are pushed into the system stack and then
a jump is taken to the specified vector location. When a software trap is executed, the
CSP for the trap service routine is loaded with the value of the VECSEG register. No
Interrupt Request flags are affected by the TRAP instruction. The interrupt service
routine called by a TRAP instruction must be terminated with a RETI (return from
interrupt) instruction to ensure correct operation.
Note: The CPU priority level and the selected register bank in PSW register are not
modified by the TRAP instruction; so, the service routine is executed with the
same priority level as the interrupt task. Therefore, the service routine entered by
the TRAP instruction can be interrupted by other traps or by higher priority
interrupts, unless triggered by a real hardware event. The service routine also
works with an unchanged register bank. If the hardware triggers the same service
routine, register bank can be selected by the ITC and may be different.
5.3.2
Hardware Traps
Hardware Traps are issued by faults or specific system states that occur during runtime
(not identified at compile time). The C166S V2 CPU distinguishes eight different
hardware trap functions. When a hardware trap condition has been detected, the CPU
branches to the trap vector location for the respective trap condition. The instruction
causing the trap event is completed before the trap handling routine is entered.
Hardware traps are not-maskable and always have a priority higher than any other CPU
task. If several hardware trap conditions are detected within the same instruction cycle,
the highest priority trap is serviced. In case of a hardware trap, the injection unit injects
an ITRAP instruction into the pipeline.
The ITRAP instruction performs the following actions:
–
Pushes PSW, CSP (in segmented mode) and IP into the System Stack
–
Sets CPU level in the PSW register to the highest possible priority level, which
disables all interrupts and DMA transfers
–
Selects the global register bank for the trap service routine
–
Branches to the trap vector location specified by the trap number of the trap condition
The eight hardware functions of the C166S V2 CPU are divided in two classes: Class A
and Class B.
Class A traps are:
–
External Non-Maskable Interrupts NMI
–
Stack Overflow
–
Stack Underflow
–
Software Break
These traps share the same trap priority, but have an individual vector address.