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參數(shù)資料
| 型號： | OV5017 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single chip 1/4 video image sensor |
| 中文描述： | 單芯片1 / 4的視頻圖像傳感器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 138K |
| 代理商： | OV5017 |
October 20, 1997
Version 1.6
7
OV5017
Confidential Preliminary Product Specification
O
MNI
V
ISION
T
ECHNOLOGIES
, Inc.
TO1
STA6
Reserved bit.
OV
STA3
Pixel data overrun flag. It is set each time pixel data is updated if
STA0 has been set already. Reading of this register clears the bit.
VSYNC
STA2
This bit duplicates the signal at pin VSYNC.
HREF
STA1
This bit duplicates the signal at pin HREF.
RDY
STA0
This bit is set each time pixel data is updated, and is cleared by read-
ing the VPORT register. This bit will not be set if the VPORT register
is being read while pixel data is updating.
FCTL
FSET
FCTL[7]
Set to initiate single frame transfer. This bit works only if FCTL[6] is
also set. If this bit is set in the middle of a frame,
HREF
will not be
asserted until the next new frame. This bit is cleared automatically at
the end of the new frame so that it can be set again.
SFR
FCTL[6]
Set to enable single frame operation mode. Since the video data is a
continuous non-stop byte stream, the validity of the data is qualified
only by assertion of
HREF
. In a continuous frame operation,
HREF
is asserted in every frame. In a single frame operation,
HREF
is
asserted only for the first frame immediately after setting the FCTL[7].
The actual duration of
HREF
assertion is programmed by the window
size.
SKIP
FCTL[3]
Makes
VSYNC
and
HREF
to skip every other frame. This function
does not alter the pixel rate; it simply blocks their assertion in every
other frame.
FBLC
FCTL[2]
Chooses how frequent the black level calibration is performed inter-
nally. It is set once every frame and cleared once every line. Line BLC
can set the BLC within a fraction of a frame time. This is useful to
speed up BLC process after power up or activation after standby
mode. However, frame BLC provides better image stability.
STOP
FCTL[1]
Set to stop chip clock and enter low power standby mode. This func-
tion does not alter register content. The chip is put in default state and
all image data is lost. Setting this bit does not prevent further register
access. Upon clearing this bit, it generally takes about two frames for
the chip to become stable.
SRST
FCTL[0]
Software reset enable. Setting this bit resets all the on-chip registers
and puts the chip in default state. Upon clearing this bit, it generally
takes about two frames for the chip to become stable.
Table 3. Bit descriptions (Continued)
Register
Name
Bit name
Range
Function
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