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參數(shù)資料
| 型號(hào)： | BW1284X |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW1284X 3.3V的12位0.32MSPS援BW1284X |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 221K |
| 代理商： | BW1284X |
SEC ASIC
bw1284x
3.3V 12BIT 0.32MSPS DAC
ANALOG
TIMING DIAGRAM
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The bw1284x has a 12bit R-string block, two decoders, two OP amps, and control block.
2. The digital outputs of two decoders decide the voltage level of R-string block.
VRT VRB
2
2
3. The voltages of VRT and VRB are internally generated by resistor strings.
(VTOP = 3.3V , VBOT = 0.0V then VRT = 2.65V , VRB= 0.65V)
For more accurate operations, you had better connect VRT and VRB with voltage sources
instead of connecting VTOP and VBOT with voltage sources. (VRT = 2.65V , VRB = 0.65V)
4. The VOUT pin is dependent of digital input values but the VHALF pin is fixed at 1.65V in normal conditions.
bw1284x is designed to drive just 10pF capacitive load.
V
(
*Dn)+VRB
Rstring
12
n
=
∑
=
DATA
VOUT
Td
000000000000
111111111111
50%
50%
VOUT
000000000000
111111111111
000000000000
10%
90%
DATA
Tr
Tf
VOUT
000000000000
111111111111
000000000000
±
0.5LSB
50%
DATA
Ts
PWDN
VOUT
Ton
50%
Toff
50%
±
0.5LSB
±
0.5LSB
0.0V
5 / 8
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