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參數(shù)資料
| 型號： | BW1227L |
| 英文描述： | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1227L 10位500KSPS / 8位650KSPS ADC的|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | BW1227L |
BW1223X
8BIT 40MSPS ADC
SEC ASIC
ANALOG
TIMING
DIAGRAM
AIN
Coarse
Sample
Coarse
Compare
FREF
COUT
Fine 1
Sample
Fine 1
Compare
Fine 2
Compare
Fine 2
Sample
MUX
OUT
FOUT
DO
A1
A2
A3
A4
A5
A0
A2
A3
A4
A0
A1
A2
A3
FComp1
FComp2
FComp2
FComp1
FComp1
A0
A1
A2
A3
A0
A1
A2
2.5 CLOCK PIPELINE DELEY
A1
7 / 11
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PDF描述 |
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| BW1220X | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1221L | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1221L_2CLK | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1221L_3CLK | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1222L | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
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