參數(shù)資料
型號： BUS-65164-180K
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
封裝： 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70
文件頁數(shù)： 36/40頁
文件大?。?/td> 349K
代理商： BUS-65164-180K
4Kx1
PROM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
SA 2
WC 0
WC 1
WC 2
WC 3
SA 3
SA 4
WC 4
SA 0
SA 1
A07
A10
A11
A08
A09
A01
A02
A03
A04
A05
BUS-65153
"STIC"
A12
A13
ILLEGAL
A10
A11
OE
BRO
T/R
D0
CLOCK
1
2
3
INCMD
CLOCK IN
OSCILLATOR
Q
D
A0 in 8-bit mode) and WRT low, followed by CS low. The sub-
system may then use the rising edge of CS to latch the data.
Similar to the DMA read operation, the address outputs A5
through A1 are incremented after the completion of a DMA
WRITE operation.
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
BUS-65153 will attempt to (1) transfer received 1553 data to the-
subsystem, (2) read data from the subsystem for transmission
on the 1553 bus, (3) transmit status (and possibly built-in-test)
information to 1553, and/or (4) set status conditions.
The BUS-65153 responds to all nonbroadcast messages with a
1553 Status Word.
RT ADDRESS
RT Address (RT_AD 4-0, (RT_AD4 = MSB)) and RT Address
Parity (RT_AD_P) should be programmed for a unique RT
address and reflect an odd parity sum. The BUS-65153 will not
respond to any MIL-STD-1553 commands or transfer received
data from any nonbroadcast messages if an odd parity sum is
not presented by RT_AD4-0 and RT_AD_P. An address parity
error will be indicated by a low output on the RT_AD_ERR pin.
The input signal RT_AD_LAT operates a transparent latch for
RTAD4-RTAD0 and RTADP. If RT_AD_LAT is low the output of
the latch tracks the value presented to the input pins. If
RT_AD_LAT is high, the output of the internal latch becomes
latched at the values presented when RT_AD_LAT was low.
COMMAND ILLEGALIZATION
The BUS-65153 provides for command illegalization. If a com-
mand is illegalized, the BUS-65153 will set the Message Error bit
and transmit its status word to the Bus Controller. No Data
Words will be transmitted in response to an illegalized Transmit
command. Data Words associated with an illegalized Receive
command will, however, be presented to the subsystem.
ILLCMD is sampled approximately 5 ms following the mid-parity
bit zero crossing of the received Command Word (reference
FIGURES 4-9). Command illegalization can be implemented
using either a two-state or three-state address bus. An external
PROM, PLD, or RAM device can be used to define the legality of
specific commands. Any subset of the possible 1553 commands
can be illegalized as a function of broadcast, T/R bit, subad-
dress, word count, and/or mode code.
Illegalizing commands in the two-state mode, based on broad-
cast, T/R bit, subaddress, and/or mode code, may be done by
means of a programmable device such as a PROM. The
address outputs from the STIC may be connected directly to the
address inputs to a PROM. Illegalizing commands in the two-
5
FIGURE 2. BUS-65153 TWO-STATE ILLEGALIZATION
相關(guān)PDF資料
PDF描述
BU-61743F3-100W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-202L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-202W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-280L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61743F3-400Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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