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參數(shù)資料
| 型號： | BUS-65164-180K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 349K |
| 代理商： | BUS-65164-180K |
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DESCRIPTION
I/O
NAME
I
O
DB_SEL
CS
8
3
TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED
DMA HANDSHAKE AND TRANSFER CONTROL (8)
O
I
O
ADDR_ENA
DT_ACK
7
2
HS_FAIL
DT_GRT
6
1
WRT
DT_REQ
4
69
INTERFACE TO 1553 PULSE TRANSFORMERS (4)
DESCRIPTION
I/O
NAME
PIN NO.
Channel A Inverted 1553 Serial Data
I/O
TX/TXA
44
Channel B Non-Inverted 1553 Serial Data.
Channel B Inverted 1553 Serial Data
Channel A Non-Inverted 1553 Serial Data
I/O
RX/TXA
40
RX/TXB
9
RX/TXB
5
Remote Terminal Address inputs.
I
34
I
RTADD03
33
RTADD02
DESCRIPTION
RT ADDRESS (8)
NAME
I
RTADD00 (LSB)
30
31
O
I
RT_ADD_P
29
RT_ADD_LAT
28
RT_ADD_ERR
27
RTADD01
31
Data Transfer Request. Active low level output signal used to inform the subsystem that the BUS-65153 needs
control of the data bus to perform a transfer. Stays low until DT_GRT is received and the transfer is completed or
until a handshake failure timeout has occurred.
Data Transfer Grant. Active low level input signal from the subsystem that, in response to a Data Transfer Request,
passes control of the parallel data bus to the BUS-65153.
Data Transfer Acknowledge - Active low level output signal used to inform the subsystem that the BUS-65153 has
received DT_GRT in response to DT_REQ. DT_ACK remains active until the transfer is complete.
Chip Select - Active low level output pulse present in the middle of every data transfer cycle. When the BUS-65153
is writing data to the subsystem, this signal occurs when the data is valid and should be used to latch the data (rec-
ommend using rising edge). When the BUS-65153 is reading data from the subsystem, this signal is used to inform
the subsystem when to drive the data bus. (Note 1)
Read/Write - Output signal that controls the direction of the data transfers. The direction is normally outward (write
= logic “0”) and only turns inward (read = logic “1”) when the first Data Word is needed from the subsystem. The
output will return low (write) after the transmission of the last data word on the 1553 bus. (Note 1)
Handshake Failure - Active low level output used to flag the subsystem that DT_GRT was not received in response
to DT_REQ in time to perform a data transfer. Latched low and cleared by the next NBGRT or RESET.
Address Enable. Active low level input signal used to control the operation of WRT, CS, and address bus A13
through A00. If a logic “0” is applied, the above signals are always active. If a logic “1” is applied, these signals are
kept in their high impedance state except for when a data transfer is being performed (DT_ACK = logic “0”)
Data Bus Select - Input signal used to select the data bus structure (8- or 16-bit width)
Logic “0” selects 16-bit data bus
Logic “1” selects 8-bit data bus
Note: For 8-bit data bus operation, D15 to D08 should be connected directly to D07 to D00, respectively.
Notes:
1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high).
2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of the received Command Word.
Remote Terminal Address [4:0] - Input signal of the address parity bit. The combination of RT_AD_[0:4], and
RT_AD_P must comprise an odd parity sum in order to enable recognition of the terminal's address.
Remote Terminal Address Latch. When low, the internal RDAD4-0 and RTADP register tracks whatever is applied
to the respective input pins. When RT_ADD_LAT is high, the information that was on RTAD4-0 and RTADP the
last time that RT_ADD_LAT was low is latched internally. The internal RTAD4-0 and RTADP are cleared to logic 0
when RESET is low.
I/O
Remote Terminal Address Parity Error Output Signal that reflects the parity combination of the RT_AD_[4:0] inputs
and RT_AD_P input. High level indicates odd parity, low level indicates even parity. Note, if RT_ADD_ERR is low,
then the BUS-65153 will not recognize any valid Command Word directed to its own RT address.
(TABLE 5 CONTINUES ON THE NEXT PAGE.)
PIN NO.
RTADD04 (MSB)
PIN NO.
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