參數(shù)資料
型號(hào): BUK9635-56
廠商: NXP Semiconductors N.V.
英文描述: TrenchMOS(TM)transistor Logic level FET(TrenchMOS(TM)晶體管邏輯電平FET)
中文描述: TrenchMOS(商標(biāo))場效應(yīng)晶體管邏輯電平(TrenchMOS(商標(biāo))晶體管邏輯電平場效應(yīng)管)
文件頁數(shù): 3/8頁
文件大小: 69K
代理商: BUK9635-56
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
BUK9635-55
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 20 A; V
DD
25 V;
V
GS
= 5 V; R
GS
= 50
; T
mb
= 25 C
MIN.
-
TYP.
-
MAX.
45
UNIT
mJ
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
0
20
40
60
80
Tmb / C
100
120
140
160
180
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1
10
100
1
10
100
1000
tp =
1 us
10us
100 us
1 ms
10ms
100ms
ID/A
VDS/V
RDS(ON) = VDS/ID
DC
0
20
40
60
80
Tmb / C
100
120
140
160
180
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1.0E-06
0.0001
0.01
t/s
1
100
0.01
0.1
1
10ZTH/ (K/W)
0.5
0.2
0.1
0.05
0.02
0
D =
t
p
t
p
T
T
P
D
t
April 1998
3
Rev 1.100
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