參數(shù)資料
型號： BUK9618-56
廠商： NXP Semiconductors N.V.
英文描述： TrenchMOS（TM）transistor Logic level FET(TrenchMOS（TM）晶體管邏輯電平FET)
中文描述： TrenchMOS（商標）場效應晶體管邏輯電平（TrenchMOS（商標）晶體管邏輯電平場效應管）
文件頁數(shù)： 1/8頁
文件大?。?/td> 68K
代理商： BUK9618-56
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
BUK9618-55
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’
trench
’ technology
thedevice features very low on-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in
automotive and general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
V
DS
I
D
P
tot
T
j
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
55
57
125
175
18
V
A
W
C
m
V
GS
= 5 V
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
mb
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
57
40
228
125
175
UNIT
V
V
V
A
A
A
W
C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 k
)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
TYP.
-
MAX.
1.2
UNIT
K/W
R
th j-a
Minimum footprint, FR4
board
50
-
K/W
d
g
s
1
3
mb
2
April 1998
1
Rev 1.000
相關PDF資料
PDF描述
BUK9621-30 TrenchMOS transistor Logic level FET
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BUK9624-56 TrenchMOS（TM）transistor Logic level FET(TrenchMOS（TM）晶體管邏輯電平FET)
BUK9628-55 TrenchMOS（TM）transistor Logic level FET(TrenchMOS（TM）晶體管邏輯電平FET)
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