參數(shù)資料
型號: BU52003GUL-E2
廠商: Rohm Semiconductor
文件頁數(shù): 12/22頁
文件大小: 505K
描述: IC HALL EFFECT SW BIPO VCSP50L1
特色產(chǎn)品: ROHM Hall Effect Sensor ICs
標(biāo)準(zhǔn)包裝: 1
傳感范圍: -5.5mT 跳閘,-0.8mT 釋放
類型: 單極開關(guān)
電源電壓: 2.4 V ~ 3.3 V
電流 - 電源: 9µA
電流 - 輸出(最大): ±1mA
輸出類型: 數(shù)字,開路集電極
特點(diǎn): 穩(wěn)壓電壓
工作溫度: -40°C ~ 85°C
封裝/外殼: 4-UFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: VCSP50L1
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1377 (CN2011-ZH PDF)
其它名稱: BU52003GUL-E2DKR
BU52002GUL,BU52003GUL,BU52012NVX,BU52012HFV,BU52013HFV
Technical Note
 
12/19
www.rohm.com
2010.08 - Rev.C
?2010 ROHM Co., Ltd. All rights reserved.
 
BU52012HFV, BU52013HFV
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
PIN No.   PIN NAME
FUNCTION
COMMENT
1
N.C.
 
OPEN or Short to GND.
2
GND
GROUND
 
3
N.C.
 
OPEN or Short to GND.
4
VDD
POWER SUPPLY
 
5
OUT
OUTPUT
 
 
螪escription of Operations
  (Micropower Operation)
 
 
 
 
 
 
 
 
 
 
 
 
 
(Offset Cancelation)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
The unipolar detection Hall IC adopts an intermittent operation
method to save energy. At startup, the Hall elements, amp,
comparator and other detection circuit power ON and magnetic
detection begins. During standby, the detection circuits power
OFF, thereby reducing current consumption. The detection results
are held while standby is active, and then output.
 
 
Reference period: 50ms (MAX100ms)
Reference startup time: 24祍
 
Fig.39
The Hall elements form an equivalent Wheatstone (resistor)
bridge circuit. Offset voltage may be generated by a differential in
this bridge resistance, or can arise from changes in resistance
due to package or bonding stress. A dynamic offset cancellation
circuit is employed to cancel this offset voltage.
When Hall elements are connected as shown in Fig. 40 and a
magnetic field is applied perpendicular to the Hall elements,
voltage is generated at the mid-point terminal of the bridge. This
is known as Hall voltage.
Dynamic cancellation switches the wiring (shown in the figure) to
redirect the current flow to a 90?angle from its original path, and
thereby cancels the Hall voltage.
The magnetic signal (only) is maintained in the sample/hold
circuit during the offset cancellation process and then released.
 
GND
V
DD
 
 
I
B
?
Hall Voltage
Fig.40
Reverse
1
2
5
3
3
Surface
 
1
4
5
2
4
 
Fig.38 
 
 
OUT
 
 
GND
 
VDD
    
TIMING LOGIC
?
HALL
ELEMENT
2
 
 
 
5
 
 
 
4
 
 
 
0.1礔 
The CMOS output terminals enable direct connection to
the PC, with no external pull-up resistor required.
 
Adjust the bypass capacitor value as
necessary, according to voltage noise
conditions, etc.
 
I
DD
Startup time
t
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