參數(shù)資料
型號(hào)： BU5071
文件頁(yè)數(shù)： 6/30頁(yè)
文件大?。?/td> 393K
代理商： BU5071
POWER-DOWN STATE
Following a period of activity in the powered-up
state the power-down state may be re-entered by
writing any of the control instructions into the serial
control port with the ”P” bit set to ”1” It is recom-
mendedthatthechip be powered down beforewrit-
ing any additional instructions. In the power-down
state, all non-essential circuitry is de-activated and
theD
X
0 andD
X
1outputsare in the high impedance
TRI-STATEcondition.
ThecoefficientsstoredintheHybridBalancecircuit
and the GainControlregisters, thedatain the LDR
and ILR, and all control bits remain unchanged in
the power-down state unless changed by writing
new data via the serial control port, which remains
operational. The outputsof the Interface Latches
alsoremain active,maintaining the ability to moni-
tor and control a SLIC.
TRANSMIT FILTER AND ENCODER
The Transmitsection input, VF
X
I, is a high imped-
ancesumming inputwhichis usedasthedifferenc-
ingpointfortheinternalhybridbalancecancellation
signal. No external componentsare needed to set
the gain. Following this circuit is a programmable
gain/attenuationamplifierwhich iscontrolledbythe
contents of the Transmit Gain Register (see Pro-
grammable Functions section). An active prefilter
then precedes the 3rd orderhigh-pass and 5th or-
der low-pass switched capacitor filters. The A/D
converterhasacompressingcharacteristicaccord-
ing to the standard CCITT A or
μ
255 coding laws,
which mustbe selectedbyacontrolinstructiondur-
inginitialization(see table1 and2). A precisionon-
chipvoltagereferenceensuresaccurateandhighly
stable transmissionlevels. Any offset voltage aris-
ing in the gain-setamplifier, the filters or the com-
paratoris cancelled byan internalauto-zerocircuit.
Each encode cycle begins immediately following
the assigned Transmit time-slot. The total signal
delay referenced to the start of thetime-slot is ap-
proximately 165
μ
s (due to the Transmit Filter)
plus 125
μ
s (due to encoding delay), which totals
290
μ
s. Data is shifted out on D
X
0 or D
X
1 during
the selected time slot on eight rising edges of
BCLK.
DECODER AND RECEIVE FILTER
PCM data is shifted into the Decoder’s Receive
PCMRegisterviathe D
R
0 orD
R
1 pinduring these-
lectedtime-sloton the 8fallingedgesof BCLK.The
Decoder consists of anexpandingDAC with either
A or
μ
255 law decodingcharacteristic,which is se-
lectedbythesame controlinstructionusedto select
the Encode law during initialization. Following the
Decoderisa 5thorderlow-passswitched capacitor
filter with integral Sin x/x correction for the 8 kHz
sample and hold. A programmable gain amplifier,
which must be set by writing to the Receive Gain
Register,isincluded,andfinallyaPost-Filter/Power
Amplifier capable of driving a 300
load to
±
3.5
V, a 600
loadto
±
3.8 V or 15 k
load to
±
4.0 V
at peak overload.
A decode cycle begins immediately after each re-
ceive time-slot, and 10
μ
s later the Decoder DAC
output is updated. The total signal delay is 10
μ
s
plus 120
μ
s (filter delay) plus 62.5
μ
s (1/2 frame)
which gives approximately190
μ
s.
PCM INTERFACE
The FS
X
andFS
R
framesyncinputs determinethe
beginning of the 8-bit transmit and receive time-
slots respectively. They may have any duration
from a single cycle of BCLK to one MCLK period
LOW. Two different relationships may be estab-
lishedbetweentheframesyncinputsandtheactual
time-slotson thePCMbussesby settingbit 3inthe
Control Register (see table 2). Non delayed data
mode is similar to long-frame timing on the
ETC5050/60 series of devices : time-slots being
nominally coincidentwith the rising edge of the ap-
propriate FS input. The alternative is to use De-
layed Data mode which is similar to short-frame
sync timing, in which each FS input must be high
at least a half-cycleof BCLKearlier than the time-
slot.
TheTime-SlotAssignmentcircuiton thedevicecan
onlybeusedwithDelayedDatatiming.Whenusing
Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate
FSinput.Theactualtransmit andreceivetime-slots
are then determined by the internalTime-Slot As-
signment counters. Transmit and Receive frames
and time-slotsmay be skewedfrom each other by
any number of BCLK cycles.
During each assigned transmit time-slot, the se-
lected D
X
0/1 output shifts data out from the PCM
register on the rising edges of BCLK. TS
X
0 (or
TS
X
1 as appropriate)also pulls low for the first 7
1/2 bit times of the time-slot to control the TRI-
STATE Enable of a backplane line driver. Serial
PCM data is shifted into the selected D
R
0/1 input
during each assigned Receive time slot on the
falling edges of BCLK. D
X
0 or D
X
1 and D
R
0 or
D
R
1 are selectable on the TS5070only.
SERIAL CONTROL PORT
Control information and data are written into or
readback from COMBO IIG via the serial control
port consistingofthecontrolclock CCLK;theserial
data input/outputCI/O (or separate input CI, and
output CO on the TS5070only) ; and the Chip Se-
lect input CS. All control instructions require 2
bytes,aslisted intable1,withtheexceptionofasin-
glebyte power-up/downcommand. The byte1 bits
are used as follows: bit 7 specifies power-up or
power-down;bits 6, 5,4 and 3 specify theregister
address;bit 2 specifies whether the instructionsis
read or write; bit 1 specifies a one or two byte in-
TS5070- TS5071
6/30
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