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參數(shù)資料
| 型號： | BU5071 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 393K |
| 代理商： | BU5071 |
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TIMINGSPECIFICATIONS
(continued)
PCM INTERFACE TIMING
Symbol
f
BCLK
Parameter
Min.
64
Typ.
Max.
4096
Unit
kHz
Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz
increments, TS5070 only)
Period of BCLK High (measured from V
IH
to V
IH
)
Period of BCLK Low (measured from V
IL
to V
IL
)
Rise Time of BCLK (measured from V
IL
to V
IH
)
Fall Time of BCLK (measured from V
IH
to V
IL
)
Hold Time, BCLK Low to FS
X/R
High or Low
Setup Time FS
X/R
High to BCLK Low
Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL
loads)
Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);
FSx Low to Dx Disabled (if BCLK8low);
BCLK9 High to Dx Disabled (if FSx still high)
Delay Time from BCLK andFSx Both High to TSx Low (Load = 100pF
plus 2 LSTTL loads)
Delay Time from BCLK8 low to TSx Disabled (if FSx alreadylow);
FSx Low to TSx Disabled
BCLK9 High to TSx Disabled
Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL
loads, applies if FSx rises later than BCLK rising edge innon-
delayed data mode only)
Setup Time, D
R
0/1 Valid to BCLK Low
Hold Time, BCLK Low to DR0/1 Invalid
t
WBH
t
WBL
t
RB
t
FB
t
HBF
t
SFB
t
DBD
80
80
ns
ns
ns
ns
ns
ns
ns
30
30
30
30
80
t
DBZ
15
80
ns
t
DBT
60
60
ns
ns
t
ZBT
(if BCLK8 low);
(if FSx still high);
15
t
DFD
80
ns
t
SDB
t
HBD
30
20
ns
ns
Figure5:
NonDelayed Data Timing (short frame mode)
TS5070- TS5071
18/30
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