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參數(shù)資料
| 型號(hào)： | BU1425AK |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | NTSC / PAL digital RGB encoder |
| 中文描述： | 的NTSC / PAL編碼器，數(shù)字RGB |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 307K |
| 代理商： | BU1425AK |
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14
Multimedia ICs
BU1425AK / BU1425AKV
Also, setting the CLKSW pin to HIGH enables the fre-
quency of the external clock to be used as BCLK, the
internal clock, just as it is. Since the data is read to the
BU1425AK / AKV at the rising edge of BCLK at this
time as well, data should be input as shown in Fig. 4.
The relationship with HSY is also as shown in Fig. 4.
HSY
VCLK
Internal clock (BCLK)
Input data
Fig. 4 Illustration of clock timing (CLKSW is HIGH)
With the BU1425AK / AKV, the sub-carrier (burst) fre-
quency is generated using the internal clock. For this
reason, the frequencies used in the various modes are
limited, so those frequencies should be input (see Table
7 below).
Table 7: BU1425AK / AKV clock input frequency settings
CLKSW Pin
Video-CD Mode
27.000MHz
13.500MHz
CD-G Mode
Same for NTSC / PAL / PAL60
NTSC
28.636MHz
14.318MHz
0
1
PAL / PAL60
28.3750MHz
14.1875MHz
5) Synchronization signals
The BU1425AK / AKV has an "Encoder Master" mode in
which synchronization signals are output, and an
"Encoder Slave" mode in which synchronization signals
are input from an external source and used to achieve
synchronization. These modes are switched at the
SLABEB pin. When the SLABEB pin is LOW, the Slave
mode is in effect, and when HIGH, the Master mode is in
effect.
In the Master mode, the HSY and VSY pins serve as out-
put, with horizontal synchronization signals (HSYNC)
being output from the HSY pin and vertical synchroniza-
tion signals (VSYNC) from the VSY pin. At this time, the
reference timing for synchronization signal output is
determined at the rising edge of the RSTB pin. Output is
obtained in accordance with the specified mode (NTSC,
PAL, or PAL60, interlace or non-interlace). Output in the
non-interlace mode, however, is output only under "Odd"
field conditions (the falling edges of Hsy and Vsy are the
same).
In the Slave mode, the HSY and VSY pins serve as input,
and horizontal synchronization signals (HSYNC) should
be input to the HSY pin and vertical synchronization sig-
nals (VSYNC) to the VSY pin. The input synchronization
signals at this time should be input in accordance with
the specified mode. With the BU1425AK / AKV, field dis-
tinction between odd and even fields is made automati-
cally for each field when interlace input is used. With the
BU1425AK, all synchronization signals are treated as
negative polarity signals (signals for which the sync inter-
val goes LOW). When using the non-interlace mode,
operation is normally carried out under odd field condi-
tions (the falling edges of Hsy and Vsy are simultane-
ous).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU1425AKV | 功能描述:IC ENCODER NTSC/PAL DGTL VQFP64 RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| BU1427K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:マルチメディアLSI |
| BU1427KV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:マルチメディアLSI |
| BU-1449-E-12-0 | 功能描述:測(cè)試引線 Black Mini-Micro-Plg RoHS:否 制造商:Pomona Electronics 設(shè)備類型:Patch Cords 連接器類型:Banana plug (stackable) on both ends 長度:60 in 顏色:Black |
| BU-1449-E-12-2 | 功能描述:測(cè)試引線 Red Mini-Micro-Plgr RoHS:否 制造商:Pomona Electronics 設(shè)備類型:Patch Cords 連接器類型:Banana plug (stackable) on both ends 長度:60 in 顏色:Black |
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