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參數(shù)資料
| 型號： | BU-65570V1-300 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, XMA |
| 封裝： | 6.3 INCH HEIGHT, VME/VXI FORMAT CARD |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 151K |
| 代理商： | BU-65570V1-300 |
5
Data Device Corporation
www.ddc-web.com
BU-65570V/65572V
F-04/05-0
DESCRIPTION
PIN
GND (connected to shell)
CH1_TXB
CH2_TXB
5
3
CH2_TXB
CH2_TXA
CH1_TXB
CH1_TXA
CH1_TXA
CH2_TXA
9
8
7
4
TABLE 4. J2 - 1553 BUS 1 & 2 CONNECTOR
2
1
6
mode commands. The BU-65570V/72V supports full RT com-
mand illegalization for each transmit or receive message based
on RT address and sub-address. In addition, individual mode
commands may be illegalized.
RT ERROR INJECTION
Error conditions may be injected on an individual RT/SA basis.
The BU-65570V/72V supports five categories of injected RT
errors: length errors, encoding errors, gap errors, status address
errors, and response errors. Length errors include both word
count errors and bit count errors. Word count errors of -32 to +1
words may be programmed. Bit counts of +3, +2, +1, -3, -2, or -
1 bit may be programmed on any word within the message.
Encoding errors are implemented though the use of two simple
yet powerful mechanisms for modifying the output of the BU-
65570V/72V's Manchester encoder. The two modifying functions
are glitch and inverse. A glitch will force the output of the
encoder to an idle bus condition for the specified period of time.
An inverse will invert the output of the encoder for the specified
period of time. The word number, starting time, and width spec-
ify the placement of this error. The error may be placed in any
word within the message. The starting time is programmed in
500 nsec increments from the beginning of the specified word.
The width of the error is specified in 50 nsec increments up to
3 μsec. This error injection scheme lends itself to generating a
host of errors including invalid sync patterns, parity errors, and
Manchester bi-phase errors.
A gap of 3, 4, or 5 μsec (measured mid parity crossing to mid-sync
crossing) may be inserted between any two words in a message.
This allows for a “dead time” gap between words of 1, 2, or 3 μsec.
A status address error may be injected in which the RT responds
with a status word containing an RT address, which does not
match the terminal's RT address. The RT may be programmed to
respond with any value from zero to 31 in its status response.
The BU-65570V/72V supports three types of response errors: no
response, a late response, or a response on the wrong bus. No
response errors may be programmed for a single bus (Bus A or
Bus B) or for both buses. Injecting a no response error on one
bus provides a simple mechanism for testing bus controller retry
conditions. A late response may be programmed in the range of
2 to 30 μsecs in 1 μsec increments.
RT INTERMESSAGE ROUTINES
The RT section of the BU-65570V/72V also supports intermes-
sage routines. Upon completion of an RT message the BU-
65570V/72V's on-board processor executes two intermessage
routines. The data table that was used by the RT for a given
message specifies which intermessage routines will be execut-
ed. Refer to TABLE 6 for a summary of the BU-65570V/72V's
intermessage routines.
BC/RT DATA TABLES
For each of the installed 1553 channels, the BU-65570V/72V
maintains 1024 data tables within the shared RAM. Each data
table may be up to 32 words in length. These data tables are
common to both BC and RT. Internal lookup tables map each RT
address, T/R, sub-address combination (RT mode) and message
number (BC mode) to a chosen data table. Data tables may be
read or written to in real time by the user and may be either sin-
gle or double buffered. Double buffering can be used to avoid the
memory access contention that occurs when the PC's application
and the 1553 bus access data tables simultaneously. The BU-
65570V/72V provides an optional block data mode in which the
data table number associated with a given BC or RT message is
incremented after completion of the message. The block data
mode is implemented as a circular data structure. Each BC mes-
sage and RT command (RT address, T/R, and sub-address) has
three data table numbers associated with it: first, last, and current.
The current data table number will be incremented after comple-
tion of a message until the value of 'last' is reached, at which point
DESCRIPTION
PIN
GND (connected to shell)
CH3_TXB
CH4_TXB
5
3
CH4_TXB
CH4_TXA
CH3_TXB
CH3_TXA
CH3_TXA
CH4_TXA
9
8
7
4
TABLE 5. J3 - 1553 BUS 3 & 4 CONNECTOR
2
1
6
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