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參數(shù)資料
| 型號： | BU-65570V1-300 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, XMA |
| 封裝： | 6.3 INCH HEIGHT, VME/VXI FORMAT CARD |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 151K |
| 代理商： | BU-65570V1-300 |
4
Data Device Corporation
www.ddc-web.com
BU-65570V/65572V
F-04/05-0
executed upon completion of the current message. The user will
define all asynchronous messages after the End-Of-Major frame
symbol and insert the message into the running frame by calling
the insert message routine. The hardware does all of the work.
BC INTERMESSAGE ROUTINES
Upon completion of a BC message, the BU-65570V/72V's on-
board processor will execute up to 2 intermessage routines.
Intermessage routines are used to implement automatic retries
on failed messages as well as other “end of message” functions.
TABLE 5 provides a summary of the BU-65570V/72V's inter-
message routines.
RESPONSE TIMEOUT
The BU-65570V/72V BC, RT's, and MT support programmable response
timeout values ranging from 2 to 29 μsecs in 1 μsec increments.
RT MODE
The BU-65570V/72V can concurrently simulate the operation of
31 unique remote terminals (RT’s) plus a broadcast address for
each of the installed channels. The BU-65570V/72V maintains
31 independent “l(fā)ast status” and “l(fā)ast command” words allowing
for full support of transmit last command and transmit status
Word Counts of -32 to +1 words may be programmed. Bit counts
of +3, +2, +1, -3, -2, or -1 bit may be programmed on any word
within the message.
Encoding errors are implemented though the use of two simple
yet powerful mechanisms for modifying the output of the BU-
65570V/72V's Manchester encoder. The two modifying functions
are glitch and inverse. A glitch error will force the output of the
encoder to an idle bus condition for the specified period of time.
An inverse error will invert the output of the encoder for the spec-
ified period of time. The word number, starting time, and width
specify the placement of the error. The error may be placed in any
word within the message and its starting time may be pro-
grammed in 500 nsec with a width of up to 3 μsec. This error injec-
tion is capable of generating a host of errors including invalid sync
patterns, parity errors, and Manchester bi-phase errors.
A gap of 3, 4, or 5 μsec (measured mid-parity crossing to mid-sync
crossing) may be inserted between any two words in a message.
This allows for a “dead time” gap between words of 1, 2, or 3 μsec.
INSERTING ASYNCHRONOUS MESSAGES
The BU-65570V/72V allows an asynchronous message to be
inserted while the card is running. The inserted message will be
TABLE 3. J1 - DISCRETE I/O, TRIGGERS, AND IRIG
DESCRIPTION
+5VDC (fuse protected)
PIN
1
IRIG Mod In
2
Chassis Ground
3
Discrete Out 16
4
Discrete Out 14
5
Discrete Out 12
6
Discrete Out 10
7
Discrete Out 8
8
Discrete Out 6
9
Discrete Out 4
10
Discrete Out 2
11
Channel 4, BC Trigger Out
12
Channel 4, BC Trigger In
13
Channel 3, BC Trigger Out
14
Channel 3, BC Trigger In
15
Channel 2, BC Trigger Out
16
Channel 2, BC Trigger In
17
Channel 1, BC Trigger Out
18
DESCRIPTION
Channel 1, BC Trigger In
PIN
19
Chassis Ground
20
IRIG (Pulse) In
21
Discrete Out 15
22
Discrete Out 13
23
Discrete Out 11
24
Discrete Out 9
25
Discrete Out 7
26
Discrete Out 5
27
Discrete Out 3
28
Discrete Out 1
29
Channel 4, Monitor Trigger Out
30
Channel 4, Monitor Trigger In
31
Channel 3, Monitor Trigger Out
32
Channel 3, Monitor Trigger In
33
Channel 2, Monitor Trigger Out
34
Channel 2, Monitor Trigger In
35
Channel 1, Monitor Trigger Out
36
Channel 1, Monitor Trigger In
37
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