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參數(shù)資料
| 型號： | BU-6486NEW |
| 英文描述： | MIL-STD-1553 Components |Mini-ACE? Mark3 |
| 中文描述： | 符合MIL - STD - 1553模塊|迷你ACE論壇？ Mark3 |
| 文件頁數(shù)： | 6/60頁 |
| 文件大?。?/td> | 410K |
| 代理商： | BU-6486NEW |
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6
Data Device Corporation
www.ddc-web.com
BU-64743/64843/64863
C-03/03-300
TRANSCEIVERS
The transceivers in the Mini-ACE Mark3 series terminals are fully
monolithic, requiring only a +3.3 volt power input. The transmit-
ters are voltage sources, providing improved line driving capabil-
ity over current sources. This serves to improve performance on
long buses with many taps. Mark3 versions with 64K x 17 RAM
offer an additional transceiver power-down (SLEEPIN) option to
further reduce device power consumption. The transmitters also
offer an option that satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +3.3 volt only transceiver requires the use of a step-
up, rather than a step-down, isolation transformer. This provides
the advantage of a higher terminal input impedance than is pos-
sible for a 15V, 12V or 5V transmitter. As a result, there is a
greater margin for the input impedance test, mandated for the
1553 validation test.This allows for longer cable lengths between
a system connector and the isolation transformers of an embed-
ded 1553 terminal.
To provide compatibility to McAir specs, the Mini-ACE Mark3 is
available with an option for transmitters with increased rise and
fall times.
The receiver sections of the Mini-ACE Mark3 are fully compliant
with MIL-STD-1553B Notice 2 in terms of front end overvoltage
protection, threshold, common-mode rejection, and word error
rate.
REGISTER AND MEMORY ADDRESSING
The software interface of the Mini-ACE Mark3 to the host proces-
sor consists of 24 internal operational registers for normal oper-
ation, an additional 24 test registers, plus 64K words of shared
memory address space.The Mini-ACE Mark3's 4K X 16 or 64K X
17 internal RAM resides in this address space.
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1F). The next 32
locations (20-3F) should be reserved, since many of these are
used for factory test.
INTERNAL REGISTERS
The address mapping for the Mini-ACE Mark3 registers is illus-
trated in TABLE 2.
BC General Purpose Queue Pointer /
RT-MT Interrupt Status Queue Pointer Register
(RD/WR)
1
1
1
1
1
BC General Purpose Flag Register (WR)
Interrupt Mask Register #2 (RD/WR)
RESERVED
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
Interrupt Status Register #2 (RD)
BC Condition Code Register (RD)
BIT Test Status Register (RD)
Configuration Register #7 (RD/WR)
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
1
1
1
1
1
Configuration Register #6 (RD/WR)
0
0
0
1
1
Test Mode Register 7
1
1
1
0
1
Test Mode Register 6
Test Mode Register 4
Test Mode Register 2
0
0
0
1
0
1
1
1
0
0
0
0
1
1
1
Test Mode Register 5
Test Mode Register 3
Test Mode Register 1
1
1
1
0
1
0
1
0
0
0
0
0
1
1
1
Test Mode Register 0
0
0
0
0
1
RT BIT Word Register (RD)
1
1
1
1
0
RT Status Word Register (RD)
0
1
1
1
0
Non-Enhanced BC Frame Time / Enhanced BC
Initial Instruction Pointer / RT Last Command /
MT Trigger Word Register(RD/WR)
1
0
1
1
0
BC Time Remaining to Next Message Register
(RD)
0
0
1
1
0
BC Frame Time Remaining Register (RD)
1
1
0
1
0
RT / Monitor Data Stack Address Register (RD)
0
1
0
1
0
Configuration Register #5 (RD/WR)
1
0
0
1
0
Configuration Register #4 (RD/WR)
0
0
0
1
0
Configuration Register #3 (RD/WR)
1
1
1
0
0
Interrupt Status Register #1 (RD)
0
1
1
0
0
Time Tag Register (RD/WR)
1
0
1
0
0
BC Control Word /
RT Subaddress Control Word Register (RD/WR)
0
0
1
0
0
Non-Enhanced BC/RT Command Stack Pointer /
Enhanced BC Instruction List Pointer Register
(RD)
1
1
0
0
0
Start/Reset Register (WR)
1
1
0
0
0
Configuration Register #2 (RD/WR)
0
1
0
0
0
Configuration Register #1 (RD/WR)
1
0
0
0
0
Interrupt Mask Register #1 (RD/WR)
0
0
0
0
0
A0
A1
A2
A3
A4
REGISTER
DESCRIPTION/ACCESSIBILITY
ADDRESS LINES
TABLE 2. ADDRESS MAPPING
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