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參數(shù)資料
| 型號(hào)： | BU-6486NEW |
| 英文描述： | MIL-STD-1553 Components |Mini-ACE? Mark3 |
| 中文描述： | 符合MIL - STD - 1553模塊|迷你ACE論壇？ Mark3 |
| 文件頁數(shù)： | 4/60頁 |
| 文件大?。?/td> | 410K |
| 代理商： | BU-6486NEW |
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4
Data Device Corporation
www.ddc-web.com
BU-64743/64843/64863
C-03/03-300
°C/W
°C
°C
°C
°C
°C
°C
in.
(mm)
in.
(mm)
oz
(g)
11
+125
+85
+70
+155
+155
+300
9
0.88 X 0.88 X 0.13
(22.3 X 22.3 X 3.3)
1.13
(28.7)
0.6
(17)
-55
-40
0
-55
-65
PHYSICAL CHARACTERISTICS
Package Body Size
80-pin Ceramic Flat pack or Gull Wing
Lead Toe-to-Toe Distance
80-pin Gull Wing
Weight
Ceramic Flat pack / Gull Wing
Package
THERMAL
Thermal Resistance,
Ceramic Flat pack / Gull Wing Package
Junction-to-Case, Hottest Die (
θ
JC
) Note 16
Operating Case Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
UNITS
MAX
TYP
MIN
PARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0.23
0.36
0.79
1.21
2.06
0.132
0.182
0.02
0.09
0.45
0.80
1.51
0.02
0.09
0.54
0.95
1.80
0.13
POWER DISSIPATION (CONT)
(NOTES 14 AND 15)
BU-64863X8-XX2 (1760)
Idle w/ transceiver SLEEPIN enabled
Idle w/ transceiver SLEEPIN disabled
25% Duty Transmitter Cycle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-64743X0-XX0, BU-64843X0-XX0
(Xcvrless)
BU-64863X0-XX0 (Xcvrless)
Hottest Die
BU-64XX3X8/9-XX0 (1553&McAir)
Idle w/ transceiver SLEEPIN enabled
(BU-64863 only)
Idle w/ transceiver SLEEPIN disabled
25% Duty Transmitter Cycle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-64XX3X8-XX2 (1760)
Idle w/ transceiver SLEEPIN enabled
(BU-64863 only)
Idle w/ transceiver SLEEPIN disabled
25% Duty Transmitter Cycle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-64XX3X0-XX0 (Xcvrless)
UNITS
MAX
TYP
MIN
PARAMETER
TABLE 1. MINI-ACE MARK3 SERIES
SPECIFICATIONS (CONT.)
MHz
MHz
MHz
MHz
%
%
%
%
%
-0.01
-0.10
0.001
0.01
60
0.01
0.10
-0.001
-0.01
40
CLOCK INPUT
Frequency:
Nominal Values
Default Mode
Option
Option
Option
Long Term Tolerance
1553A Compliance
1553B Compliance
Short Term Tolerance, 1 second
1553A Compliance
1553B Compliance
Duty Cycle
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of First
Message for Non-enhanced BC Mode
16.0
12.0
10.0
20.0
μs
μs
μs
μs
μs
μs
μs
μs
μs
19.5
23.5
51.5
131
7
17.5
21.5
49.5
127
4
BC Intermessage Gap (Note 8)
Non-enhanced (Mini-ACE compatible)
BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout (Note 10)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
2.5
9.5
10
to 10.5
18.0
22.5
50.5
129.5
660.5
TABLE 1 Notes:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Receiver Differential Input Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
(2)
Impedance parameters are specified directly between pins
TX/RX_A(B) and TX/RX_A(B) of the Mini-ACE Mark3 hybrid.
(3)
It is assumed that all power and ground inputs to the hybrid are con-
nected.
(4)
The specifications are applicable for both unpowered and powered
conditions.
(5)
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input.The applicable frequency range is 75 kHz to 1 MHz.
(6)
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7)
Assumes a common-mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8)
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 μs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM and 5 dur-
ing EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 μs
with a 12 MHz clock, 4.5 μs with a 16 MHz clock, or 3.6 μs with a
20 MHz clock.
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