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參數資料
| 型號： | BR24L04FJ-W |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 512】8 bit electrically erasable PROM |
| 中文描述： | 512】8位電可擦除可編程ROM |
| 文件頁數： | 8/25頁 |
| 文件大?。?/td> | 388K |
| 代理商： | BR24L04FJ-W |
BR24L04-W / BR24L04F-W / BR24L04FJ-W
Memory ICs
BR24L04FV-W / BR24L04FVM-W
z
Device operation
1) Start condition (Recognition of start bit)
All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING)
2) Stop condition (Recognition of stop bit)
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH. (See Fig.4 SYNCHRONOUS DATA TIMING)
3) Notice about write command
In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory.
4) Device addressing
Following a START condition, the master output the slave address to be accessed.
The most significant four bits of the slave address are the “device type identifier”, for this device it is fixed as “1010”.
The next two bit (device address) identify the specified device on the bus.
The device address is defined by the state of A1 and A2 input pins. This IC works only when the device address
inputted from SDA pin correspond to the state of A1 and A2 input pins. Using this address scheme, up to four
devices may be connected to the bus. The next bit (PS) is used by the master to select two 256 word page of
memory.
PS set to “0” - - - - - - 1page (000 to 0FF)
PS set to “1” - - - - - - 2page (100 to 1FF)
The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
R / W set to “0” - - - - - - WRITE (including word address input of Random Read)
R / W set to “1” - - - - - - READ
8/25
5) Write protect (WP)
When WP pin set to V
CC
(H level), write protect is set for 512 words (all address).
When WP pin set to GND (L level), enable to write 512 words (all address).
Either control this pin or connect to GND (or V
CC
). It is inhibited from being left unconnected.
A2
A1
PS
1010
R / W
相關PDF資料 |
PDF描述 |
|---|---|
| BR24L04FV-W | 512】8 bit electrically erasable PROM |
| BR24L04FVM-W | 512】8 bit electrically erasable PROM |
| BR2505W | RO Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 3.3V; Output Voltage (Vdc): 24V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85% |
| BR2510W | ECONOLINE: ROM - Micro Size SIP4 Package- 3kVDC Isolation- Industry Standard Pinout- UL94V-0 Package Material- Custom Solutions Available- Cost Effective- Efficiency to 85% |
| BR2510W | TECHNICAL SPECIFICATIONS OF SINGLE-PHASE SILICON BRIDGE RECTIFIER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| BR24L04FJ-WE2 | 功能描述:電可擦除可編程只讀存儲器 SRL 512X8 BIT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| BR24L04FJ-WTR | 制造商:ROHM 制造商全稱:Rohm 功能描述:High Reliability Series EEPROMs I2C BUS |
| BR24L04FVJ-WE2 | 制造商:ROHM Semiconductor 功能描述:EEPROM SERIAL-I2C 4K-BIT 512 X 8 2.5V/3.3V/5V 8-PIN TSSOP-BJ - Tape and Reel 制造商:ROHM Semiconductor 功能描述:EEPROM Serial-2Wire 4K-bit 512 x 8 2.5V/3.3V/5V 8-Pin TSSOP-BJ T/R Cut Tape 制造商:ROHM Semiconductor 功能描述:IC EEPROM 4KBIT 400KHZ 8TSSOP |
| BR24L04FVJ-WTR | 制造商:ROHM 制造商全稱:Rohm 功能描述:High Reliability Series EEPROMs I2C BUS |
| BR24L04FVM-W | 制造商:ROHM 制造商全稱:Rohm 功能描述:512】8 bit electrically erasable PROM |
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