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參數(shù)資料
| 型號： | BR24L01 |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | 128】8 bit electrically erasable PROM |
| 中文描述： | 128】8位電可擦除可編程ROM |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 391K |
| 代理商： | BR24L01 |
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BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
Memory ICs
BR24L01AFV-W / BR24L01AFVM-W
13/25
z
Application
1) WP effective timing
WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to
[
WP effective timing
]
as follows.
During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective
period.
The period from the start condition to the rising edge of the clock which take in D0 of the data (the first byte of the data
for Page Write) is the cancellation invalid period. WP input is don’t care during the period. Setup time for rising edge of
the SCL which takes in D0 must be more than 100ns.
The period from the rising edge of SCL which takes in D0 to the end of internal write cycle (t
WR
) is the cancellation
effective period. In case of setting WP to “H” during t
WR
, WRITE operation is stopped in the middle and the data of
accessing address is not guaranteed, so that write correct data again please.
It is not necessary waiting t
WR
(5msmax.) after stopping command by WP, because the device is stand by state.
S
T
A
R
T
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
DATA
D7
D6
D5
D4
D3
D2
D1
D0
SDA
WP
tWR
WP cancellation invalid period
WP cancellation effective period
No data will be written
Stop of the write
operation
Data is not
guaranteed
SCL
SDA
D1
D0
ACK
AN ENLARGEMENT
·
The rising edge of the clock
which take in D0
SCL
SDA
D0
ACK
AN ENLARGEMENT
·
The rising edge
of SDA
Fig.13 WP EFFECTIVE TIMING
相關(guān)PDF資料 |
PDF描述 |
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| BR24L04F-W | 512】8 bit electrically erasable PROM |
| BR24L04FJ-W | 512】8 bit electrically erasable PROM |
| BR24L04FV-W | 512】8 bit electrically erasable PROM |
| BR24L04FVM-W | 512】8 bit electrically erasable PROM |
| BR2505W | RO Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 3.3V; Output Voltage (Vdc): 24V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BR24L01A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| BR24L01AFJ-W | 制造商:ROHM 制造商全稱:Rohm 功能描述:128】8 bit electrically erasable PROM |
| BR24L01AFJ-WE2 | 功能描述:電可擦除可編程只讀存儲器 SRL 128X8 BIT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| BR24L01AFVJ-W | 制造商:ROHM 制造商全稱:Rohm 功能描述:I2C BUS 1Kbit (128 x 8bit) EEPROM |
| BR24L01AFVJ-WE2 | 功能描述:IC EEPROM SER 1KBIT I2C 8TSSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:256K (32K x 8) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:28-TSSOP（0.465"，11.8mm 寬） 供應(yīng)商設(shè)備封裝:28-TSOP 包裝:帶卷 (TR) 其它名稱:71V256SA15PZGI8 |
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