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參數(shù)資料
| 型號： | BR24E16 |
| 廠商： | Rohm CO.,LTD. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 298K |
| 代理商： | BR24E16 |
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
Memory Ics
BR24C16FJ /
BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
(5) Write protect (WP)
When WP pin set to V
CC
(High level), write protect is set by all address. When WP pin set to GND (Low level), enable
to write to all address. Either control this pin or connect to GND (or V
CC
). It is inhibited from being left unconnected.
(6) ACK signal
The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer
is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data output
(
μ
-COM when a write or read command of the slave address input ; this IC when reading data).
For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is
sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address
input,
μ
-COM when a read command data output).
The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8
bits).
When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each 8 bits
of data (word address and write data).
When data is being read from the IC, 8bits of data (read data) are output and the IC waits for a returned LOW
acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not
sent from the master (
μ
-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not
detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop
bit). The IC then enters the waiting or standby state.
(See Fig.3 for acknowledge signal (ACK signal) response.)
1
8
9
SCL
(from
μ
-COM)
SDA
SDA
Start condition
(start bit)
Acknowledge signal
(ACK signal)
output data)
(
μ
COM
(IC output data)
Fig.3 Acknowledge (ACK signal) response
(during write and read slave address input)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BR24E16F | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| BR24E16FJ | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| BR24E16FV | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| BR24L02FV-W | 256x8 bit electrically erasable PROM |
| BR24L02FVM-W | 256x8 bit electrically erasable PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BR24E16F | 制造商:ROHM 制造商全稱:Rohm 功能描述:I2C BUS compatible serial EEPROM |
| BR24E16FJ | 制造商:ROHM 制造商全稱:Rohm 功能描述:I2C BUS compatible serial EEPROM |
| BR24E16FV | 制造商:ROHM 制造商全稱:Rohm 功能描述:I2C BUS compatible serial EEPROM |
| BR24G01-3 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Serial EEPROM Series Standard EEPROM I2C BUS EEPROM (2-Wire) |
| BR24G01-3A | 制造商:ROHM 制造商全稱:Rohm 功能描述:Serial EEPROM series Standard EEPROM |
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