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參數(shù)資料
| 型號： | BD9153MUV-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 630K |
| 描述： | IC REG TRPL BCK/LINEAR 24VQFN |
| 特色產(chǎn)品： | CMOS LDO Regulators |
| 標準包裝： | 1 |
| 拓撲： | 降壓（降壓）同步（2），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 3 |
| 頻率 - 開關： | 1MHz |
| 電壓/電流 - 輸出 1： | 1.8 V ~ 3.3 V，1.5A |
| 電壓/電流 - 輸出 2： | 0.8 V ~ 2.5 V，1.5A |
| 電壓/電流 - 輸出 3： | 控制器 |
| 帶 LED 驅動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-VQFN |
| 包裝： | 標準包裝 |
| 其它名稱： | BD9153MUV-E2DKR |
Technical Note
15/18
www.rohm.com
2009.08 - Rev.A
?2009 ROHM Co., Ltd. All rights reserved.
BD9153MUV
?SPAN class="pst BD9153MUV-E2_2471427_7">BD9153MUV Cautions on PC Board layout
Fig.42 Layout diagram
` Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to
the pin PGND.
a Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
; VQFN024V4040 (BD9153MUV) has thermal PAD on the reverse of the package.
The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB.
?SPAN class="pst BD9153MUV-E2_2471427_7">Recommended components Lists on above application
Symbol
Part
Value
Manufacturer
Series
L1,2 Coil
2.2礖
TDK LTF5022-2R2N3R2
CIN1,CIN2 Ceramic capacitor
22礔
Murata GRM32EB11A226KE20
Cout1,Cout2 Ceramic capacitor
22礔
Murata GRM31CB30J226KE18
CITH1 Ceramic capacitor
VOUT1=3.3V 680pF Murata GRM18 Series
RITH1 Resistance
VOUT1=3.3V 39k&
Rohm MCR03 Series
CITH2 Ceramic capacitor
VOUT2=1.2V 680pF Murata GRM18 Series
RITH2 Resistance
VOUT2=1.2V 12k&
Rohm MCR03 Series
Cfb Ceramic capacitor
56pF
Murata GRM18 Series
M1 Nch MOS FET
-
Rohm RTF015N03
;The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit
characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to
accommodate variations between external devices and BU9153MUV when employing the depicted circuit with other
circuit constants modified. Both static and transient characteristics should be considered in establishing these margins.
When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and
PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
Silk screen
Top Layer
Bottom Layer
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