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參數(shù)資料
| 型號： | BD7851FP-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 25-HSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 恒定電流： | 是 |
| 拓?fù)洌?/td> | 線性 |
| 輸出數(shù)： | 16 |
| 內(nèi)部驅(qū)動器： | 是 |
| 類型 - 主要： | 通用 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 輸出電壓： | 10V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 25-SOP（0.213"，5.40mm）+ 2 翼片 |
| 供應(yīng)商設(shè)備封裝： | 25-HSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 工作溫度： | -30°C ~ 85°C |
| 產(chǎn)品目錄頁面： | 1372 (CN2011-ZH PDF) |
| 其它名稱： | BD7851FP-E2DKR |
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
9/24
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
【BU2092F/BU2092FV】
●Pin descriptions
●Timing chart
Fig. 4
1.
After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into
the DATA terminal.
2.
Qx parallel output data of the shift register is set after the 12
th clock by the LCK.
3.
Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
4.
Data retained in the internal latch circuit is output when the OE is in the “L” section.
［Truth Table］
Input
Function
CLOCK
DATA
LCK
OE
×
H
Output (Q0～Q11) Disable
×
L
Output (Q0～Q11) Enable
L
×
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
H
×
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
×
The data of shift register has no change.
×
The data of shift register is transferred to the storage register.
×
The data of storage register has no change.
Pin No.
Pin Name
I/O
Function
1
VSS
-
GND
2
DATA
I
Serial Data Input
3
CLOCK
I
Shift clock of DATA (Rising Edge Trigger)
4
LCK
I
Latch clock of DATA (Rising Edge Trigger)
5～11,
14～18
Q0～Q11
O
Parallel Data Output (Nch Open Drain FET)
Latch Data
L
H
Output FET
ON
OFF
12, 13
N.C.
-
Non connected
17
OE
I
Output Enable (“H” level : output FET is OFF)
18
VDD
-
Power Supply
CLOCK
LCK
DATA
DATA11
DATA10
DATA9
DATA1
DATA0
OE
Qx
Previous DATA
DATA11～0
“H”
Note) Diagram shows a status where a pull-up resistor is connected to output.
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