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參數(shù)資料
| 型號： | BD3504FVM-TR |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 605K |
| 描述： | IC REG CTRLR SGL POS ADJ 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 正，可調(diào)式 |
| 輸出數(shù)： | 1 |
| 輸出電壓： | 0.65 V ~ 2.5 V |
| 輸入電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -10°C ~ 100°C |
| 封裝/外殼： | 8-VSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
BD3504FVM,BD3500FVM,BD3501FVM,BD3502FVM
Technical Note
9/16
www.rohm.com
2010.05 - Rev.A
?2010 ROHM Co., Ltd. All rights reserved.
?SPAN class="pst BD3504FVM-TR_2649171_6">Pin Function Descriptions
鸙CC
BD3500/01/02/04FVM has an independent power input pin for an internal circuit operation of IC. This is used for bias of
IC internal circuit and external N-MOSFET. The voltage used of VCC terminal is 5.0V and maximum current is 1.7 mA.
It is recommended to connect a bypass capacitor of 0.1 礔 or so to VCC pin.
鸈N
With an input of 2.0 volts or higher, the EN terminal turns to High level and VOUT is outputted. At 0.8V or lower, it
detects Low level and VOUT is turned OFF and simultaneously, the discharge circuit inside the VS terminal is activated
and lowers output voltage (150 mA (Min) when VFB//VS=1V and VEN=0V).
鸙IN(BD3500/01/02FVM)
The VIN terminal is a drain voltage detection terminal of external N-MOSFET. In the event that the VIN terminal is lower
than 1.1 times the output set voltage, output is turned OFF to prevent low-input maloperation.
鸙D(BD3504FVM only)
The VD terminal is a drain voltage detection terminal of external N-MOSFET. In the event that drain voltage (VIN) is low,
output voltage is turned OFF to prevent low-input maloperation. The reset voltage (VDUVLO) of drain voltage low-input
maloperation prevention circuit is determined by the following equation:
In the event that the maloperation prevention set resistance at the time of low-input drain voltage is set to a resistance
value same as output voltage set resistor (R1 = R1, R2 = R2), low-input maloperation prevention (UVLO) is reset when
drain voltage (VIN) reaches 70% of the output voltage. UVLO detects only at the startup of the EN terminal.
鸙FB(BD3504FVM only)
The VFB terminal is a terminal to decide output voltage and is determined by the following equation:
VFB is controlled to achieve 0.65 V (typ.).
鸑RCS terminal
he NRCS terminal is a constant current output terminal, and operates as
?Soft-Start ... during start-up
桽CP-Delay ... after start-up (BD3504FVM only).
How to set Soft-Start of NRCS terminal
The output voltage startup time (TNRCS) is determined by the time when the NRCS terminal reaches VFB (0.65V).
During start-up, the NRCS terminal serves as a constant current source (INRCS) of 20 礎(chǔ) (Typ.) output, and charges
capacitor (CNRCS) externally connected. By changing over to internal reference voltage (0.65V) when the NRCS
terminal reaches 0.65V, output voltage (VOUT) is fixed.
How to set NRCS terminal short protection Delay (BD3504FVM only)
BD3504FVM has short protection (SCP) activated when output voltage becomes VOUT x 0.35 (typ.) or lower. The
time when short protection is activated until latching takes place (TSCP) is determined by the following equation:
Tscp = CNRCS ?Voscp ?Iscp
When short protection is activated, the NRCS terminal provides 20 礎(chǔ) (typ.) constant current output (lscp), and charges
the capacitor (CNRCS) externally connected. When the NRCS terminal reaches 1.3V (Voscp), latch operation is
carried out and output voltage is turned OFF.
鸖CP(BD3500/01/02FVM)
BD3500/01/02FVM has short protection (SCP) activated when output becomes 70% or lower than the set voltage. The
time when short protection is activated until latching takes place (T
SCP
) is determined by the following equation:
Tscp = CNRCS ?Voscp ?Iscp
When short protection is activated, the NRCS terminal provides 20 礎(chǔ) (typ.) constant current output (lscp), and charges
the capacitor (CNRCS) externally connected. When the NRCS terminal reaches 1.3V (Voscp), latch operation is carried
out and output voltage is turned OFF.
鸙FB//VS (BD3500FVM/BD3501FVM/BD3502FVM//BD3504FVM)
VFB//VS terminal is a source voltage detection terminal of external N-MOSFET. VFB//VS terminal has the internal
discharge circuit activated to lower output voltage when EN becomes a Low level or various protection circuits (TSD, SCP,
UVLO) are activated.
鸊
G terminal is a gate drive terminal of external N-MOSFET. Because the output voltage range of G terminal is up to 5V
(VCC), it is necessary to use N-MOSFET whose threshold is lower than 5V-VOUT. In addition, by incorporating a RC
snubber circuit to the G terminal, phase allowance of loop gain can be increased and the terminal can accommodate
ceramic capacitors.
VDUVLO=VFB?.7?
R1 +R2
R1
VOUT=VFB?
R1 +R2
R1
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