- 您現(xiàn)在的位置：買賣IC網 > Datasheet目錄39 > BD3504FVM-TR (Rohm Semiconductor)IC REG CTRLR SGL POS ADJ 8MSOP Datasheet資料下載
參數(shù)資料
| 型號： | BD3504FVM-TR |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 605K |
| 描述： | IC REG CTRLR SGL POS ADJ 8MSOP |
| 標準包裝： | 2,000 |
| 類型： | 正，可調式 |
| 輸出數(shù)： | 1 |
| 輸出電壓： | 0.65 V ~ 2.5 V |
| 輸入電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -10°C ~ 100°C |
| 封裝/外殼： | 8-VSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
BD3504FVM,BD3500FVM,BD3501FVM,BD3502FVM
Technical Note
14/16
www.rohm.com
2010.05 - Rev.A
?2010 ROHM Co., Ltd. All rights reserved.
10. Output capacitor (C5)
Connect the output capacitor between Vo1, Vo2 terminals and GND terminal without fail in order to stabilize output voltage.
The output capacitor has a role to compensate for the phase of loop gain and to reduce output voltage fluctuation when
load is rapidly changed. When there is an insufficient capacity value, there is a possibility to cause oscillation, and when
the equivalent serial resistance (ESR) of the capacitors is large, output voltage fluctuation is increased when load is rapidly
changed. About 220 礔 high-performance electrolytic capacitors are recommended, but this greatly depends on the gate
capacity of external MOSFET and mutual conductance (gm), temperature and load conditions. In addition, when only
ceramic capacitors with low ESR are used, or various capacitors are connected in series, the total phase allowance of loop
gain becomes not sufficient, and oscillation may result. Thoroughgoing confirmation at application temperature and
under load range conditions is requested.
11. Input capacitor setting method (C1, C4)
The input capacitor plays a part to lower output impedance of a power supply connected to input terminals (Vcc, VIN).
When output impedance of this power supply increases, the input voltages (Vcc, VIN) become unstable and there is a
possibility of giving rise to oscillation and degraded ripple rejection characteristics. The use of capacitors of about 10 礔
with low ESR, which provide less capacity value changes caused by temperature changes, is recommended, but since
input capacitor greatly depends on characteristics of the power supply used for input, substrate wiring pattern, and
MOSFET gate-drain capacity, thoroughgoing confirmation under the application temperature, load range, and M-MOSFET
conditions is requested.
12. NRCS terminal capacitor setting method (C3)
To the present IC, there mounted is a function (Non Rush Current on Start-up: NRCS) to prevent rush current from VIN to
load and output capacitor via Vo at the output voltage start-up. When the EN terminal is reset from Hi or UVLO, constant
current is allowed to flow from the NRCS terminal. By this current, voltage generated at the NRCS terminal becomes the
reference voltage and output voltage is started. In order to stabilize the NRCS set time, it is recommended to use a
capacitor (B special) with less capacity value change caused by temperature change.
13. SCP terminal capacitor setting method (C2)
The present IC incorporates a timer-latch type short-circuit protection circuit in order to prevent MOSFET from being
destroyed by abnormal current when output terminal is short-circuited (operates at the time of NRCS, too). When the
output terminal voltage drops 30% from output setting voltage, IC judges that the output is short-circuited. In such event,
constant current begins to flow. When the voltage generated in the SCP terminal reaches 1.3V (Typ) by this current, the
gate terminal is brought to the Low level. In order to stabilize the SCP setting time, a capacitor (B special) with less
capacity value change caused by temperature changes is recommended. When the SCP function is not used,
short-circuit the SCP terminal to the GND terminal. In addition, when the output terminal is short-circuited, the MOSFET
gate voltage reaches the Vcc voltage and the large current that meets MOSFET characteristics flows to the output while
the timer latch type protection circuit operates. When the current capacity of VIN terminal power supply lacks, the Vin
terminal voltage lowers and the UVLO circuit operates, and the latch operation may not be finished. In such event,
connect a limiting resistor across drain terminal and VIN terminal of MOSFET.
14. Input terminals (VCC, VIN, EN)
In the present IC, N terminal, VIN terminal, and VCC terminal have an independent construction. In addition, in order to
prevent malfunction at the time of low input, the UVLO function is equipped with the VIN terminal and the VCC terminal.
They begin to start output voltage when all the terminals reach threshold voltage without depending on the input order of
input terminals.
15. Maximum output current (maximum load)
The maximum output current capacity of the power supply which is composed by the use of the present IC depends on the
external FET. Consequently, confirm the characteristics of the power required for the set to be used, choose the external
FET.
16. Operating ranges
If it is within the operating ranges, certain circuit functions and operations are warranted in the working ambient
temperature range. With respect to characteristic values, it is unable to warrant standard values of electric
characteristics but there are no sudden variations in characteristic values within these ranges.
17. Allowable loss Pd
With respect to the allowable loss, the thermal derating characteristics are shown in the Exhibit, which we hope would be
used as a good-rule-of-thumb. Should the IC be used in such a manner to exceed the allowable loss, reduction of current
capacity due to chip temperature rise, and other degraded properties inherent to the IC would result. You are strongly
urged to use the IC within the allowable loss.
18. The use in the strong electromagnetic field may sometimes cause malfunction, to which care must be taken.
19.In the event that load containing a large inductance component is connected to the output terminal, and generation of
back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.
20. We are certain that examples of applied circuit diagrams are recommendable,
but you are requested to thoroughly confirm the characteristics before using the IC.
In addition, when the IC is used with the external circuit changed, decide the IC
with sufficient margin provided
while consideration is being given not only to static characteristics but also
variations of external parts and our IC including transient characteristics.
OUTPUT PIN
(Example)
相關PDF資料 |
PDF描述 |
|---|---|
| BD3521FVM-TR | IC REG CTRLR SGL 1.5V MSOP8 |
| BD9153MUV-E2 | IC REG TRPL BCK/LINEAR 24VQFN |
| CAT2300VP2-GT3 | IC SENSE FET CONTROLLER 8TDFN |
| CAT34TS02VP2GT4A | IC TEMP SENSOR 2K MEMORY 8TDFN |
| CAT6095VP2-GT4 | IC TEMP SENSOR STAND ALONE 8TDFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| BD3505 | 制造商:WTE 制造商全稱:Won-Top Electronics 功能描述:35A BOSCH TYPE PRESS-FIT DIODE |
| BD3506 | 制造商:WTE 制造商全稱:Won-Top Electronics 功能描述:35A BOSCH TYPE PRESS-FIT DIODE |
| BD3506EFV | 制造商:ROHM 制造商全稱:Rohm 功能描述:Nch FET Ultra LDO for PC Chipsets |
| BD3506F | 制造商:ROHM 制造商全稱:Rohm 功能描述:Nch FET Ultra LDO for PC Chipsets |
| BD3506F_08 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Ultra Low Dropout Linear Regulators for PC Chipsets |
發(fā)布緊急采購，3分鐘左右您將得到回復。