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參數(shù)資料
| 型號： | B9940L |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| 中文描述： | 2.5V或3.3V，200兆赫，1:18時鐘分配緩沖區(qū) |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 201K |
| 代理商： | B9940L |
B9940L
Document #: 38-07105 Rev. *C
Page 3 of 5
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
:............ V
SS
– 0.3V
Maximum Input Voltage Relative to V
DD
:.............V
DD
+ 0.3V
Storage Temperature: ................................–65
°
C to + 150
°
C
Operating Temperature:................................–40
°
C to +85
°
C
Maximum ESD protection...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDC
= 3.3V ±5% or 2.5V ±5%, T
A
= –40°C to +85°C
Parameter
V
IL
V
IH
I
IL
I
IH
V
PP
V
CMR
Description
Conditions
Min.
V
SS
2.0
–
–
500
Typ.
–
–
–
–
–
–
–
–
–
–
2
Max.
0.8
V
DD
–200
200
1000
V
DD
– 0.6
V
DD
– 0.6
0.5
–
–
5
Unit
V
V
μA
μA
mV
V
V
V
V
V
mA
Input Low Voltage
Input High Voltage
Input Low Current
[3]
Input High Current
[3]
Peak-to-Peak Input Voltage PECL_CLK
Common Mode Range
[4]
PECL_CLK
All other inputs
All other inputs
V
DD
= 3.3V
V
DD
= 2.5V
I
OL
= 20 mA
I
OH
= –20 mA, V
DDC
= 3.3V
I
OH
= –20 mA, V
DDC
= 2.5V
V
DD
– 1.4
V
DD
– 1.0
–
2.4
1.8
–
V
OL
V
OH
Output Low Voltage
[5]
Output High Voltage
[5]
I
DDQ
Z
out
Quiescent Supply Current
Output Impedance
V
DD
= 3.3V
V
DD
= 2.5V
9
11
–
14
18
4
19
26
–
C
in
Input Capacitance
pF
AC Parameters
V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDC
= 3.3V ±5% or 2.5V ±5%, T
A
= –40°C to +85°C
[6]
Parameter
Description
F
max
Maximum Input Frequency
t
PD
V
DD
= 3.3V
V
DD
= 2.5V
t
PD
V
DD
= 3.3V
V
DD
= 2.5V
FoutDC
Output Duty Cycle
[7, 8, 9]
Measured at V
DD
/2
T
skew
V
DD
= 3.3V, Fin = 150 MHz
V
DD
= 2.5V, Fin = 150 MHz
T
skew
(pp)
PECL, V
DDC
= 3.3V
PECL, V
DDC
= 2.5V
Notes:
2.
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power suppl sequencing is NOT required.
3.
Inputs have pull-up/pull-down resistors that effect input current.
4.
The V
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V
CMR
range and the input lies within the V
specification.
5.
Driving series or parallel terminated 50
(or 50
to V
/2) transmission lines.
6.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7.
Outputs driving 50
transmission lines.
8.
50% input duty cycle.
9.
Outputs loaded with 30 pF each.
10. Across temperature and voltage ranges, includes output skew.
Conditions
Min.
–
2.0
2.6
1.8
2.3
45
–
–
–
–
Typ.
–
3.5
4.0
3.3
3.8
–
–
–
–
–
Max.
200
4.0
5.2
3.8
4.4
55
150
200
1.4
2.2
Units
MHz
ns
PECL_CLK to Q Delay
[7, 9]
TTL_CLK to Q Delay
[7, 9]
ns
%
ps
Output-to-Output Skew
[7, 9]
Part-to-Part Skew
[10]
ns
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