
AZ10LVE111
AZ100LVE111
ECL/PECL 1:9 Differential Clock Driver
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Operating Range of 3.0V to 5.5V
Low Skew
Guaranteed Skew Spec
Differential Design
V
BB
Output
75k
Ω
Internal Pulldown Resistors
Direct Replacement for ON
Semiconductor MC100LVE111
DESCRIPTION
The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The
IN signal is fanned-out to nine identical differential outputs.
The AZ100LVE111 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the V
BB
reference should be connected to one side of the IN/ˉˉ
differential input pair. The input signal is then fed to the other IN/ˉˉ input. When used, the V
bypassed to ground via a 0.01
μ
F capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent t
pd
distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50
Ω
, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same V
CCO
) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
BB
pin should be
PACKAGE AVAILABILITY
PART NO.
PACKAGE
MARKING
AZ10
LVE111
<Date Code>
AZ100
LVE111
<Date Code>
AZ100+
LVE111
<Date Code>
NOTES
PLCC 28
AZ10LVE111FN
1,2
PLCC 28
AZ100LVE111FN
1,2
PLCC 28 RoHS
Compliant / Lead
(Pb) Free
1
Add R2 at end of part number for 13 inch (750 parts) Tape & Reel.
2
Date code format: “YY” for year followed by “WW” for week.
AZ100LVE111FN
+
1,2