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參數(shù)資料
| 型號： | AZ100LVE210 |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL 1:4, 1:5 Differential Clock Driver |
| 中文描述： | ECL / PECL的1:4，1:5差分時鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 79K |
| 代理商： | AZ100LVE210 |
AZ100LVE210
ECL/PECL 1:4, 1:5 Differential Clock Driver
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Operating Range of 3.0V to 5.5V
Low Skew
Guaranteed Skew Spec
Differential Design
V
BB
Output
75k
Ω
Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC100LVE210 & MC100E210
DESCRIPTION
The AZ100LVE210 is a low skew 1:4, 1:5 fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system skew. The AZ100LVE210 offers two
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.
The AZ100LVE210 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the V
BB
reference should be connected to one side of the CLKa/CLKb
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The V
BB
should only be used as a
bias for its sink/source capability is limited. When used, the V
BB
pin should be bypassed to ground via a 0.01
μ
F
capacitor.
Both sides of the differential output must be terminated into 50
Ω
to ensure that the tight skew specification is
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the
same V
CCO
) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being
catastrophic to most designs this will result in an increase in skew.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
AZM100LVE210
<Date Code>
NOTES
PLCC 28
AZ100LVE210FN
1,2
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AZ100LVE210FN | ECL/PECL 1:4, 1:5 Differential Clock Driver |
| AZ100LVE310 | ECL/PECL 2:8 Differential Clock Driver |
| AZ100LVE310FN | ECL/PECL 2:8 Differential Clock Driver |
| AZ100LVEL11T | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ10EL11D | ECL/PECL 1:2 Differential Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AZ100LVE210FN | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 1:4, 1:5 Differential Clock Driver |
| AZ100LVE310 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 2:8 Differential Clock Driver |
| AZ100LVE310FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ECL/PECL 2:8 Differential Clock Driver |
| AZ100LVE310FNR2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ECL/PECL 2:8 Differential Clock Driver |
| AZ100LVEL11 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 1:2 Differential Fanout Buffer |
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