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參數(shù)資料
| 型號： | AZ10EP16VST |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL Differential Receiver with Variable Output Swing |
| 中文描述： | ECL / PECL的差分接收器輸出變秋千 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 131K |
| 代理商： | AZ10EP16VST |
AZ10EP16VS
AZ100EP16VS
ECL/PECL Differential Receiver with Variable Output Swing
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Silicon-Germanium for High Speed
Operation
150ps Typical Propagation Delay
AZ100EP16VS Functionally Equivalent
to ON Semiconductor MC100EP16VS
at 3.3V
Available in a 3x3mm MLP Package
S-Parameter (.s2p) and IBIS Model Files
available on Arizona Microtek Website
DESCRIPTION
The AZ10/100EP16VS is a Silicon–Germanium (SiGe) differential receiver with variable output swing. The
EP16VS has functionality and output transition times similar to the EP16, with an input that controls the amplitude
of the Q/Q outputs.
Connecting the BOOST pin to V
EE
increases the output swing by about 15% above standard ECL/PECL levels.
The BOOST pin is internally tied to V
EE
for the SOIC 8 and TSSOP 8 packages, and is under external user control
for the MLP 16 package. When both the BOOST pin and the V
CTRL
pin are not connected, the part operates with the
standard ECL/PECL output and V
BB
levels of the AZ10/100EP16 device. To ensure best performance, the BOOST
pin should be tied to V
EE
when the variable swing feature is used.
The operational range of the EP16VS control input, V
CTRL
, is from V
REF
(full swing) to V
CC
(min. swing).
Maximum swing is achieved by leaving the V
CTRL
pin open or tied to V
EE
. Simple control of the output swing can be
obtained by a variable resistor between the V
REF
and V
CC
pins, with the wiper driving V
CTRL
. Typical application
circuits and results are described in this Data Sheet.
The EP16VS provides a V
REF
(V
BB
/V
REF
) output for a DC bias when AC coupling to the device. The V
REF
pin
should be used only as a bias for the EP16VS as its current sink/source capability is limited. Whenever used, the
V
REF
pin should be bypassed to ground via a 0.01
μ
F capacitor.
Under open input conditions for D/D, the Q/Q outputs are not guaranteed.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
AZM10
EP16VS
AZM100
EP16VS
AZTP
EP16VS
AZHP
EP16VS
AZM
16S
<Date Code>
AZM+
16S
<Date Code>
NOTES
SOIC 8
AZ10EP16VSD
1,2,3
SOIC 8
AZ100EP16VSD
1,2,3
TSSOP 8
AZ10EP16VST
1,2,3
TSSOP 8
AZ100EP16VST
1,2,3
MLP 16 (3x3)
AZ10/100EP16VSL
1,2
MLP 16 (3x3)
RoHS Compliant /
Lead(Pb) Free
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2
Date code format: “Y” or “YY” for year followed by “WW” for week.
3
Date code “YWW” or “YYWW” on underside of part.
AZ10/100EP16VSL+
1,2
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