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參數(shù)資料
| 型號： | AZ100LVEL32DG |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL ± 2 Divider |
| 中文描述： | ECL / PECL的± 2分頻 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 186K |
| 代理商： | AZ100LVEL32DG |
AZ10LVEL32
AZ100LVEL32
ECL/PECL
÷
2 Divider
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Operating Range of 3.0V to 5.5V
470ps Propagation Delay
3.0GHz Toggle Frequency
High Bandwidth Output Transitions
Direct Replacement for ON
Semiconductor MC10EL/LVEL32 &
MC100EL/LVEL32
DESCRIPTION
The AZ10/100LVEL32 is an integrated
÷
2 divider. The reset pin is asynchronous and is asserted on the rising
edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization
of multiple LVEL32’s in a system.
The LVEL32 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the V
BB
reference should be connected to one side of the CLK/ˉˉˉˉ differential
input pair. The input signal is then fed to the other CLKˉˉˉˉ input. The V
BB
pin should be used only as a bias for
the LVEL32 as its sink/source capability is limited. When used, the V
BB
pin should be bypassed to ground via a
0.01
μ
F capacitor.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
1
4
3
2
6
5
7
8
R
÷2
RESET
CLK
CLK
V
BB
V
CC
Q
Q
V
EE
PIN DESCRIPTION
FUNCTION
CLK, ˉˉˉ
Clock Inputs
RESET
Asynchronous Reset
V
BB
Reference Voltage Output
Q, Q
Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
PIN
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
SOIC 8 Green /
RoHS Compliant /
Lead (Pb) Free
TSSOP 8 Green /
RoHS Compliant /
Lead (Pb) Free
MLP 8 (2x2) Green
/ RoHS Compliant /
Lead (Pb) Free
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2
Date code format: “Y” or “YY” for year followed by “WW” for week on
underside of part.
3
Date code format: “Y” for year followed by “WW” for week.
MARKING
NOTES
AZ100LVEL32DG
AZM100G
LVEL32
1,2
AZ100LVEL32TG
AZHG
LV32
1,2
AZ100LVEL32NG
C2G
<Date Code>
1,3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AZ100LVEL32NG | ECL/PECL ± 2 Divider |
| AZ100LVEL32TG | ECL/PECL ± 2 Divider |
| AZ10LVEL32 | ECL/PECL ± 2 Divider |
| AZ100LVEL33 | ECL/PECL ±4 Divider |
| AZ100LVEL33D | ECL/PECL ±4 Divider |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AZ100LVEL32NG | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ÷ 2 Divider |
| AZ100LVEL32T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ECL/PECL ÷ 2 Divider |
| AZ100LVEL32TG | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ÷ 2 Divider |
| AZ100LVEL33 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ±4 Divider |
| AZ100LVEL33_11 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ÷4 Divider |
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