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參數(shù)資料
| 型號： | AZ100LVEL33D |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL ±4 Divider |
| 中文描述： | ECL / PECL的± 4分頻 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 136K |
| 代理商： | AZ100LVEL33D |
AZ10LVEL33
AZ100LVEL33
ECL/PECL
÷
4 Divider
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Green / RoHS Compliant /
Lead (Pb) Free package available
Operating Range of 3.0V to 5.5V
470ps Propagation Delay
4.0GHz Toggle Frequency
Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC10EL33, MC100EL33,
and MC100LVEL33
Transistor Count = 91 Devices
IBIS Model Files Available on Arizona
Microtek Web Site
DESCRIPTION
The AZ10/100LVEL33 is an integrated
÷
4 divider. The RESET pin is asynchronous and clears the output (Q
Low, Q High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET
allows for the synchronization of multiple LVEL33’s in a system.
The LVEL33 provides a V
BB
output for single-end use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the V
BB
reference should be connected to one side of the CLK/ ˉˉˉˉ differential
input pair. The input signal is then fed to the other CLK ˉˉˉˉ input. The V
BB
pin can support 1.0mA sink/source
current. When used, the V
BB
pin should be bypassed to ground via a 0.01
μ
F capacitor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM
R
÷4
RESET
CLK
CLK
V
BB
Q
Q
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MLP 8 (2x2) Green
/ RoHS Compliant /
Lead (Pb) Free
MARKING
NOTES
AZ100LVEL33NG
C3G
<Date Code>
1,2
MLP 16 (3x3)
AZ10/100LVEL33L
AZM
L33
<Date Code>
AZM10
LVEL33
AZM100
LVEL33
AZT
LV33
AZH
LV33
1,2
SOIC 8
AZ10LVEL33D
1,2,3
SOIC 8
AZ100LVEL33D
1,2,3
TSSOP 8
AZ10LVEL33T
1,2,3
TSSOP 8
AZ100LVEL33T
1,2,3
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K
parts) Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
Date code “YWW” or “YYWW” on underside of part.
2
3
PIN DESCRIPTION
PIN
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
CLK, ˉˉˉ
RESET
V
BB
Q, Q
V
CC
V
EE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AZ100LVEL33NG | ECL/PECL ±4 Divider |
| AZ100LVEL33T | ECL/PECL ±4 Divider |
| AZ10LVEL33 | ECL/PECL ±4 Divider |
| AZ10LVEL33D | ECL/PECL ±4 Divider |
| AZ10LVEL33T | ECL/PECL ±4 Divider |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AZ100LVEL33DG | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ÷4 Divider |
| AZ100LVEL33NG | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ±4 Divider |
| AZ100LVEL33T | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ±4 Divider |
| AZ100LVEL33TG | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL ÷4 Divider |
| AZ100LVEL58 | 制造商:AZM 制造商全稱:AZM 功能描述:PECL/ECL 2:1 Multiplexer |
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