參數(shù)資料
型號： AZ100LVEL16VTND
廠商： Arizona Microtek, Inc.
英文描述： ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
中文描述： ECL / PECL的振蕩器的增益級
文件頁數(shù)： 1/13頁
文件大?。?/td> 225K
代理商： AZ100LVEL16VTND
AZ100LVEL16VT
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
P9
<Date Code>
NOTES
MLP 8 (2x2x0.75)
AZ100LVEL16VTNA
1,2,3
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNA+
P9+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTNB
P8
<Date Code>
1,2,4
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNB+
P8+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTNC
P2
<Date Code>
1,2,5
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNC+
P2+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTND
P3
<Date Code>
1,2
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTND+
P3+
<Date Code>
1,2
MLP 16 (3x3)
AZ100LVEL16VTL
AZM
16T
<Date Code>
AZM+
16T
<Date Code>
N/A
1,2
MLP 16 (3x3) RoHS
Compliant / Lead (Pb)
Free
DIE
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2
Date code format: “Y” or “YY” for year followed by “WW” for week.
3
Parts marked TNA for date codes prior to 4WW (prior to 2004).
4
Parts marked TNB for date codes prior to 4WW (prior to 2004).
5
Parts marked TNC for date codes prior to 4WW (prior to 2004).
6
Waffle Pack
AZ100LVEL16VTL+
1,2
AZ100LVEL16VTXP
6
FEATURES
High Bandwidth for
≥
1GHz
Similar Operation as
AZ100LVEL16VR except in
Disabled Condition: Q
HG
is High
Operating Range of 3.0V to 5.5V
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a 3x3 mm or 2x2 mm
MLP Package
S-Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
DESCRIPTION
The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable.
The Q
HG
/Q
HG
outputs have a voltage gain several times greater than the Q/Q outputs.
MLP 16, 3x3 mm Package (VTL) or DIE (VTX)
The AZ100LVEL16VTL and AZ100LVEL16VTX provide a selectable enable input (EN) that allows
continuous oscillator operation. See truth table for the Enable function. If Enable pull-up is desired in the
CMOS/TTL mode, an external
≤
20 k
Ω
resistor connecting EN to V
CC
will override the on-chip pull-down resistor.
When disabled, the Q
HG
output is forced high and the Q
HG
output is forced low. The AZ100LVEL16VTL/VTX also
provides a V
BB
and 470
Ω
internal bias resistors from D to V
BB
and D to V
BB
. The V
BB
pin can support 1.5 mA
sink/source current. Bypassing V
BB
to ground with a 0.01
μ
F capacitor is recommended.
The outputs Q and Q each have a selectable on-chip pull-down current source. See truth table below for current
source functions. External resistors may also be used to increase pull-down current to a maximum total of 25 mA.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AZ100LVEL16VTND+ 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
AZ100LVEL16VTXP 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
AZ100LVEL16VV 制造商:AZM 制造商全稱:AZM 功能描述:Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
AZ100LVEL16VV_12 制造商:AZM 制造商全稱:AZM 功能描述:Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable
AZ100LVEL16VVL+ 制造商:AZM 制造商全稱:AZM 功能描述:Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
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