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參數(shù)資料
| 型號： | AXDA1600DUT3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | OPGA-453 |
| 文件頁數(shù)： | 97/106頁 |
| 文件大小： | 2275K |
| 代理商： | AXDA1600DUT3C |
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78
Pin Descriptions
Chapter 11
AMD Athlon XP Processor Model 8 Data Sheet
25175H—March 2003
Preliminary Information
K7CLKOUT and
K7CLKOUT# Pins
K7CLKOUT and K7CLKOUT# are each run for two to three
inches and then terminated with a resistor pair: 100 ohms to
VCC_CORE and 100 ohms to VSS. The effective termination
resistance and voltage are 50 ohms and VCC_CORE /2.
Key Pins
These 16 locations are for processor type keying for forwards
and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29).
Motherboard designers should treat key pins like NC (No
Connect) pins. A socket designer has the option of creating a
top mold piece that allows PGA key pins only where designated.
However, sockets that populate all 16 key pins must be allowed,
so the motherboard must always provide for pins at all key pin
locations.
See “NC Pins” for more information.
NC Pins
The motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin
NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins
No pin is present at pin locations A1 and AN1. Motherboard
designers should not allow for a PGA socket pin at these
locations.
For more information, see the AMD Athlon Processor-Based
Motherboard Design Guide, order# 24363.
PLL Bypass and Test
Pins
PLLT EST#, PLLBYPA S S#, PLLMON1, PLLMON2 ,
PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass
and test interface. This interface is tied disabled on the
motherboard. All six pin signals are routed to the debug
connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup
resistors.
PWROK Pin
The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
For more information, Chapter 9, “Signal and Power-Up
相關PDF資料 |
PDF描述 |
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| AXH010A0X3 | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| AXK5S30047YG | AXK5S(P5KS) Socket(0.5mm pitch, 30-pin, Ni-barrier) (RoHS conforming); Height: For H=4,5,6mm |
| AXK5S30347YG | AXK5S(P5KS) Socket(0.5mm pitch, 30-pin, Ni-barrier) (RoHS conforming); Height: For H=7,8,9mm |
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| AXK5S40347YG | AXK5S(P5KS) Socket(0.5mm pitch, 40-pin, Ni-barrier) (RoHS conforming); Height: For H=7,8,9mm |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AXDA2800DKV4D | 制造商:Advanced Micro Devices 功能描述:MPU AMD Athlon XP 64-Bit 0.13um 2.083GHz 453-Pin OPGA |
| AXDBG-2-GEVK | 功能描述:AX8052F1 - Debugger 制造商:on semiconductor 系列:- 零件狀態(tài):有效 類型:調(diào)試程序 配套使用產(chǎn)品/相關產(chǎn)品:AX8052F1 內(nèi)容:板 標準包裝:1 |
| AXE | 制造商:Velleman Inc 功能描述: |
| AXE.25A | 制造商:Distributed By MCM 功能描述:AGX 1'' x 1/4'' |
| AXE10 | 制造商:AXTAL 制造商全稱:AXTAL 功能描述:SMD PXO (Clock) in CO 26 package |
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