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參數(shù)資料
| 型號： | AX88655AB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5-Port 10/100/1000BASE-T Ethernet Switch |
| 中文描述： | 5端口10/100/1000BASE-T以太網(wǎng)交換機 |
| 文件頁數(shù)： | 8/33頁 |
| 文件大?。?/td> | 266K |
| 代理商： | AX88655AB |
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COL1
CRS1
RX_DV1
RX_CLK1
RXD1[7:0]
ASIX ELECTRONICS CORPORATION
8
AX88655AB 5-Port 10/100/1000BASE-T Ethernet Switch
CONFIDENTIAL
I/PD
I/PD
I
I
I/PD E20, F17, F18,
F19, F20, G17,
G18, G19
D18
D19
E19
E18
Collision Detect:
Please references section 2.1.1.
Carrier Sense:
Please references section 2.1.1.
Receive Data Valid:
Please references section 2.1.1.
Receive Clock Input:
Please references section 2.1.1.
Receive Data:
Please references section 2.1.1.
2.1.6 RGMII/GMII/MII Interface Port 2
Signal Name
I/O
GTX_CLK2
O
TX_EN2
TXD2[7:0]
Pin No.
A18
Description
125MHz Clock Output:
Please references section 2.1.1.
O
B18
Transmit Enable:
Please references section 2.1.1.
O
C18, B19, A19,
A20, B20, C19,
C20, D20
C15
D15
D14
A15
B15
I/PD D16, C16, B16,
A16, D17,
C17, B17, A17
Transmit Data:
Please references section 2.1.1.
TX_CLK2
COL2
CRS2
RX_DV2
RX_CLK2
RXD2[7:0]
I/PD
I/PD
I/PD
I
I
MII Transmit Clock Input:
Please references section 2.1.1.
Collision Detect:
Please references section 2.1.1.
Carrier Sense:
Please references section 2.1.1.
Receive Data Valid:
Please references section 2.1.1.
Receive Clock Input:
Please references section 2.1.1.
Receive Data:
Please references section 2.1.1.
2.1.7 RGMII/GMII/MII Interface Port 3
Signal Name
I/O
GTX_CLK3
O
TX_EN3
TXD3[7:0]
Pin No.
A11
Description
125MHz Clock Output:
Please references section 2.1.1.
O
C12
Transmit Enable:
Please references section 2.1.1.
O
B12, A12, C13,
B13, A13, C14,
B14, A14
D9
C8
D8
B9
C9
A9, D10, C10,
B10, A10,
D11, C11, B11
Transmit Data:
Please references section 2.1.1.
TX_CLK3
COL3
CRS3
RX_DV3
RX_CLK3
RXD3[7:0]
I/PD
I/PD
I/PD
I
I
I/PD
MII Transmit Clock Input:
Please references section 2.1.1.
Collision Detect:
Please references section 2.1.1.
Carrier Sense:
Please references section 2.1.1.
Receive Data Valid:
Please references section 2.1.1.
Receive Clock Input:
Please references section 2.1.1.
Receive Data:
Please references section 2.1.1.
2.1.8 RGMII/GMII/MII Interface Port 4
Signal Name
I/O
GTX_CLK4
O
TX_EN4
O
Pin No.
A5
Description
125MHz Clock Output:
Please references section 2.1.1.
B5
Transmit Enable:
Please references section 2.1.1.
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