
1.0 AX88655AB Overview
1.1 General Description
The AX88655AB Gigabit switch controller supports eight 10/100/1000 Mbps ports in wire-speed operation. The
AX88655AB Gigabit switch controller provides eight 10/100/1000 Ethernet ports with RGMII/GMII/MII interface. For
each ports, the AX88655AB supports GMII/RGMII (802.3ab, 1000BASE-T) interface with full-duplex operation at
Gigabit speed, full- or half-duplex operation at 10/100 Mbps speed (using 802.3/u, 10/100BASE-T) and polls the status
of PHYs with an embedded MPU.
The device supports 4K internal MAC addresses which are shared by all ports with an embedded SRAM. The
learning/routing engine is implemented with a two-way hash/linear algorithm to reduce possibility of routing collision.
Basically the AX88655AB supports non-blocking wire speed forwarding rate and no Head-of-Line (HOL) blocking
issue. The AX88655AB provides two flow-control mechanisms to avoid loss of data: an optional jamming based
backpressure flow control in the half-duplex operation and IEEE 802.3x in the full-duplex mode.
To support Quality of Service (QoS), each output port has two priority queues and their assignment can be based on the
802.1p priority field or Port-Pair setting. Each output port retrieves the frames from the shared buffer based on queuing
and sends them to the transmitting (Tx) FIFO.
1.2 AX88655AB Block Diagram
Fig-1 AX88655AB Block Diagram
ASIX ELECTRONICS CORPORATION
5
AX88655AB 5-Port 10/100/1000BASE-T Ethernet Switch
CONFIDENTIAL
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
High Speed
Switch Fabric
Routing /Learning
Engine
Buffer Manager
Packet
Buffer
General Purpose
I/O Interface (GPIO)
Address Look-up Table
10/100/1000 MAC
EEPROM
Interface
GPIO
Configuration
Logic
RGMII/GMII PHY
RGMII/GMII PHY
RGMII/GMII PHY
RGMII/GMII PHY
RGMII/GMII PHY