參數(shù)資料
型號: ATWEBDVK-02WC
廠商: Atmel
文件頁數(shù): 98/137頁
文件大小: 0K
描述: KIT DEV TCP/IP AT89C51RD2 WEBCAM
標準包裝: 1
系列: @Web
主要目的: *
嵌入式: *
已用 IC / 零件: AT89C51RD2
主要屬性: *
次要屬性: *
已供物品: 板,帶網(wǎng)絡 Webcam 模塊和軟件
產(chǎn)品目錄頁面: 617 (CN2011-ZH PDF)
63
4235K–8051–05/08
AT89C51RD2/ED2
16. Serial Port Interface (SPI)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communica-
tion between the MCU and peripheral devices, including other MCUs.
16.1
Features
Features of the SPI Module include the following:
Full-duplex, three-wire synchronous transfers
Master or Slave operation
Eight programmable Master clock rates
Serial clock with programmable polarity and phase
Master Mode fault error flag with MCU interrupt capability
Write collision flag protection
16.2
Signal Description
Figure 16-1 shows a typical SPI bus configuration using one Master controller and many Slave
peripherals. The bus is made of three wires connecting all the devices.
Figure 16-1. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel port to
control the four SS pins of the Slave devices.
16.2.1
Master Output Slave Input (MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-
nal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
16.2.2
Master Input Slave Output (MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-
nal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
Slave 1
M
IS
O
M
O
S
I
S
C
K
S
MISO
MOSI
SCK
SS
P
O
R
T
0
1
2
3
Slave 3
M
IS
O
M
O
S
I
S
C
K
S
Slave 4
M
IS
O
M
O
S
I
S
C
K
S
Slave 2
M
IS
O
M
O
S
I
S
C
K
S
VDD
Master
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