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參數(shù)資料
| 型號： | ATV750 |
| 廠商： | Atmel Corp. |
| 英文描述： | High-density UV Erasable Programmable Logic Device(高密度紫外線可擦除PLD) |
| 中文描述： | 高密度的紫外線可擦除可編程邏輯器件（高密度紫外線可擦除可編程邏輯器件） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 495K |
| 代理商： | ATV750 |
1
Features
Third Generation Programmable Logic Structure
– High-density Replacement for Discrete Logic
High-speed – Plus a New, Low Power Version
Increased Logic Flexibility
– 42 Inputs and 20 Sum Terms
Flexible Output Logic
– 20 Flip-flops - 10 Extra
– All Can be Individually Buried or 10 Output Directly
– Each has Individual Asynchronous Reset and Clock Terms
Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
Proven and Reliable High-speed CMOS EPROM Process
– 2000V ESD Protection
– 200 mA Latchup Immunity
Reprogrammable
– Tested 100% for Programmability
24-pin, 300-mil Dual-In-line and 28-lead Surface Mount Packages
Logic Diagram
Description
The ATV750(L) is 100% more powerful than most other programmable logic devices
in 24-pin packages. Increased product terms, sum terms, and flip-flops translate into
more usable gates.
Each of the ATV750(L)’s twenty-two logic pins can be used as an input. Ten of these
can be used as input, output, or bi-directional I/O pins. All twenty flip-flops can be fed
back into the array independently. This flexibility allows burying all of the sum terms
and flip-flops.
There are 171 product terms available. A variable format is used to assign between
four and eight product terms per sum term. There are two sum terms per output,
providing added flexibility.
Rev. 0024G–03/00
Pin Configurations
Pin Name
Function
IN
Logic Inputs
I/O
Bi-directional Buffers
*
No Internal Connection
VCC
+5V Supply
(continued)
High-density UV
Erasable
Programmable
Logic Device
ATV750
ATV750L
Commercial and
industrial versions
are obsolete. Please
use ATF750C.
Military versions are
migrating to
ATV750B(L), but please
do not use for new
designs. For new
military applications,
recommend multiple
ATF22V10s.
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
PLCC/LCC
(Top View)
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
*
IN
IN
IN
I/O
I/O
I/O
*
I/O
I/O
I/O
4
3
2
1
2
2
2
1
1
1
1
1
1
1
I
I
G
*
I
I
I
I
I
I
*
V
I
I
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