參數(shù)資料
型號: ATSAM3X8EA-CU
廠商: Atmel
文件頁數(shù): 60/71頁
文件大小: 0K
描述: IC MCU 2X256KB CORTEX-M3 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: SAM3X
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 84MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,LIN,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 103
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 100K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LFBGA
包裝: 托盤
65
11057BS–ATARM–13-Jul-12
SAM3X/A
65
11057BS–ATARM–13-Jul-12
SAM3X/A
128-byte transmit FIFO and 128-byte receive FIFO
Automatic pad and CRC generation on transmitted frames
Automatic discard of frames received with errors
Address checking logic supports up to four specific 48-bit addresses
Support Promiscuous Mode where all valid received frames are copied to memory
Hash matching of unicast and multicast destination addresses
Physical layer management through MDIO interface
Half-duplex flow control by forcing collisions on incoming frames
Full-duplex flow control with recognition of incoming pause frames
Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged
Frames
Multiple buffers per receive and transmit frame
Jumbo frames up to 10,240 bytes supported
12.14 True Random Number Generator (TRNG)
Passed NIST Special Publication 800-22 Tests Suite
Passed Diehard Random Tests Suite
Provides a 32-bit Random Number Every 84 Clock Cycles
12.15 External Bus Interface (EBI)
Only present on 144-pin version of SAM3X
Managing SMC, Nand Flash accesses offering:
– Up to 8 Configurable chip select
– Programmable timing on a per chip select basis
– 16-Mbyte Address Space per Chip Select
– 8- or 16-bit Data Bus
– Word, Halfword, Byte Transfers
– Byte Write or Byte Select Lines
– Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select
– Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select
– Programmable Data Float Time per Chip Select
– External Wait Request
– Automatic Switch to Slow Clock Mode
– Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to
32 Bytes
– NAND Flash Controller supporting NAND Flash with Multiplexed Data/Address
buses
– Supports SLC NAND Flash technology
– Supports Hardware Error Correcting Code (ECC), 1-bit error correction, 2-bit error
detection
– Detection and Correction by Software
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