參數(shù)資料
型號(hào): ATSAM3X8EA-CU
廠商: Atmel
文件頁數(shù): 53/71頁
文件大?。?/td> 0K
描述: IC MCU 2X256KB CORTEX-M3 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: SAM3X
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 84MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,LIN,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 103
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 100K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LFBGA
包裝: 托盤
59
11057BS–ATARM–13-Jul-12
SAM3X/A
59
11057BS–ATARM–13-Jul-12
SAM3X/A
12. Embedded Peripherals Overview
12.1
Serial Peripheral Interface (SPI)
Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
– Four Character FIFO in Reception
Connection to DMA Channel Capabilities Optimizes Data Transfers
– One channel for the Receiver, One Channel for the Transmitter
12.2
Two Wire Interface (TWI)
Master, Multi-Master and Slave Mode Operation
Compatibility with Atmel two-wire interface, serial memory and I
2C compatible devices
One, two or three bytes for slave address
Sequential read/write operations
Bit Rate: up to 400 kbit/s
General Call Supported in Slave Mode
SMBUS Quick Command Supported in Master Mode
Connection to Peripheral DMA Controller (PDC) for TWI0 and TWI1 and DMA Controller
(DMAC) for TWI0 Channel Capabilities Optimizes Data Transfers in Master Mode Only
12.3
Universal Asynchronous Receiver Transceiver (UART)
Two-pin UART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
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