參數(shù)資料
型號: ATSAM3SD8CA-CU
廠商: Atmel
文件頁數(shù): 18/57頁
文件大小: 0K
描述: IC MCU 2X256KB CORTEX-M3 100-QFN
標準包裝: 260
系列: SAM3S
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 64MHz
連通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 79
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: *
包裝: *
25
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
7.5
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in the following table.
7.6
Peripheral DMA Controller
Handles data transfer between peripherals and memories
Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-3.
SAM3S8_SD8 Master to Slave Access
Slaves
Masters
0
1
2
3
Cortex-M3 I/D
Bus
Cortex-M3 S
Bus
PDC
CRCCU
0
Internal SRAM
-
X
1
Internal ROM
X
-
X
2
Internal Flash
X
-
X
3
External Bus Interface
-
X
4
Peripheral Bridge
-
X
-
Table 7-4.
Peripheral DMA Controller
Instance name
Channel T/R
USART2
Transmit
USART2
Receive
PWM
Transmit
TWI1
Transmit
TWI0
Transmit
UART1
Transmit
UART0
Transmit
USART1
Transmit
USART0
Transmit
DACC
Transmit
SPI
Transmit
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