參數(shù)資料
型號(hào): ATSAM3S-EK2
廠商: Atmel
文件頁數(shù): 32/57頁
文件大?。?/td> 0K
描述: EVAL KIT FOR SAM3S8 & SAM3SD8
設(shè)計(jì)資源: SAM3S-EK2 Design & Mfg Files
SAM3S-EK2 Design & Mfg Files Information
SAM3S-EK2 Demo Release Notes
標(biāo)準(zhǔn)包裝: 1
類型: MCU
適用于相關(guān)產(chǎn)品: ATSAM3S 系列
所含物品:
38
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
10.13 Chip Identification
Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
JTAG ID: 0x05B2D03F
10.14 UART
Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
10.15 PIO Controllers
3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79
I/O Lines
Each PIO Controller controls up to 32 programmable I/O Lines
Fully programmable through Set/Clear Registers
Multiplexing of four peripheral functions per I/O Line
For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change interrupt
– Programmable Glitch filter
– Programmable debouncing filter
– Multi-drive option enables driving in open drain
– Programmable pull-up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
– Additional interrupt modes on a programmable event: rising edge, falling edge, low
level or high level
Table 10-1.
SAM3S8/SD8 Hip IDs Register
Chip Name
Flash Size
(KBytes)
Pin Count
CHIPID_CIDR
CHIPID_EXID
SAM3S8B (Rev A)
512
64
0x289B0A60
0x0
SAM3S8C (Rev A)
512
100
0x28AB0A60
0x0
SAM3SD8B (Rev A)
512
64
0x299B0A60
0x0
SAM3SD8C (Rev A)
512
100
0x29AB0A60
0x0
Table 10-2.
PIO available according to pin count
Version
64 pin
100 pin
PIOA
32
PIOB
15
PIOC
-32
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