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| 型號： | ATMEGA64M1-MU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU AVR 64K FLASH 32QFN |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction megaAVR Introduction |
| 標(biāo)準(zhǔn)包裝： | 2,080 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | CAN，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 11x10b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 包裝： | 托盤 |
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
11 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
CSA
16
7
5
E1
I
Chip Select A, B, C, D (active LOW). This function is
associated with the 16 mode only, and for individual
channels ‘A’ through ‘D’. When in 16 mode, these pins
enable data transfers between the user CPU and the
SC16C654B/654DB for the channel(s) addressed. Individual
UART sections (A, B, C, D) are addressed by providing a
logic 0 on the respective CSA to CSD pin. When the
68 mode is selected, the functions of these pins are
re-assigned. 68 mode functions are described under their
respective name/pin headings.
CSB
20
11
9
G1
CSC
50
38
31
G9
CSD
54
42
35
E9
CTSA
11
2
1
C1
I
Clear to Send (active LOW). These inputs are associated
with individual UART channels A through D. A logic 0 on the
CTS pin indicates the modem or data set is ready to accept
transmit data from the SC16C654B/654DB. Status can be
tested by reading MSR[4]. This pin only affects the transmit
or receive operations when Auto CTS function is enabled via
the Enhanced Feature Register EFR[7] for hardware ow
control operation.
CTSB
25
16
12
J2
CTSC
45
33
26
K10
CTSD
59
47
-
B10
D0 to D2,
D3 to D7
66 to 68
, 1to5
53 to 55,
56 to 60
39 to 41,
42 to 46
B7, A7,
B6, A6,
B5, A5,
B4, A4
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-state
data bus for transferring information to or from the controlling
CPU. D0 is the least signicant bit and the rst data bit in a
transmit or receive serial data stream.
DSRA
10
1
-
B1
I
Data Set Ready (active LOW). These inputs are associated
with individual UART channels, A through D. A logic 0 on this
pin indicates the modem or data set is powered-on and is
ready for data exchange with the UART. This pin has no
effect on the UART’s transmit or receive operation.
DSRB
26
17
-
K1
DSRC
44
32
25
K9
DSRD
60
48
-
B9
DTRA
12
3
-
D1
O
Data Terminal Ready (active LOW). These outputs are
associated with individual UART channels, A through D. A
logic 0 on this pin indicates that the SC16C654B/654DB is
powered-on and ready. This pin can be controlled via the
modem control register. Writing a logic 1 to MCR[0] will set
the DTR output to logic 0, enabling the modem. This pin will
be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
This pin has no effect on the UART’s transmit or receive
operation.
DTRB
24
15
-
J1
DTRC
46
34
27
J10
DTRD
58
46
-
C9
GND
6, 23,
40, 57
14, 28,
45, 61
21, 37, 47 B3, K7,
H1, D9
I
Signal and power ground.
INTA
15
6
4
D2
O
Interrupt A, B, C, D (active HIGH). This function is
associated with the 16 mode only. These pins provide
individual channel interrupts INTA to INTD. INTA to INTD are
enabled when MCR[3] is set to a logic 1, interrupts are
enabled in the interrupt enable register (IER), and when an
interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer
empty, or when a modem status ag is detected. When the
68 mode is selected, the functions of these pins are
re-assigned. 68 mode functions are described under their
respective name/pin headings.
INTB
21
12
10
G2
INTC
49
37
30
G10
INTD
55
43
36
D10
Table 2:
Pin description …continued
Symbol
Pin
Type Description
PLCC68 LQFP64 HVQFN48 LFBGA6
4
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