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參數(shù)資料
| 型號： | ATMEGA64M1-MU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU AVR 64K FLASH 32QFN |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction megaAVR Introduction |
| 標(biāo)準(zhǔn)包裝： | 2,080 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | CAN，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 11x10b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 包裝： | 托盤 |
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
10 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
Type Description
PLCC68 LQFP64 HVQFN48 LFBGA6
4
16/68
31
-
14
-
I
16/68 Interface type select (input with internal pull-up).
This input provides the 16 (Intel) or 68 (Motorola) bus
interface type select. The functions of IOR, IOW,
INTA to INTD, and CSA to CSD are re-assigned with the
logical state of this pin. When this pin is a logic 1, the
16 mode interface (16C654) is selected. When this pin is a
logic 0, the 68 mode interface (68C654) is selected. When
this pin is a logic 0, IOW is re-assigned to R/W, RESET is
re-assigned to RESET, IOR is not used, and INTA to INTD
are connected in a wire-OR conguration. The wire-OR
outputs are connected internally to the open-drain IRQ
signal output. This pin is not available on 64-pin packages
which operate in the 16 mode only.
A0
34
24
17
K5
I
Address 0 select bit. Internal registers address selection in
16 and 68 modes.
A1
33
23
16
J5
I
Address 1 select bit. Internal registers address selection in
16 and 68 modes.
A2
32
22
15
K4
I
Address 2 select bit. Internal registers address selection in
16 and 68 modes.
A3
20
-
9
-
I
Address 3, Address 4 select bits. When the 68 mode is
selected, these pins are used to address or select individual
UARTs (providing CS is a logic 0). In the 16 mode, these
pins are re-assigned as chip selects, see CSB and CSC.
These pins are not available on 64-pin packages which
operate in the 16 mode only.
A4
50
-
31
-
CDA9
64
-
A1
I
Carrier Detect (active LOW). These inputs are associated
with individual UART channels A through D. A logic 0 on this
pin indicates that a carrier has been detected by the modem
for that channel.
CDB
27
18
-
K2
CDC
43
31
24
J9
CDD
61
49
-
A10
CLKSEL
30
-
I
Clock Select. The 1
× or 4× pre-scalable clock is selected by
this pin. The 1
× clock is selected when CLKSEL is a logic 1
(connected to VCC) or the 4× is selected when CLKSEL is a
logic 0 (connected to GND). MCR[7] can override the state
of this pin following reset or initialization (see MCR[7]). This
pin is not available on 64-pin packages which provide
MCR[7] selection only.
CS
16
-
5
-
I
Chip Select (active LOW). In the 68 mode, this pin
functions as a multiple channel chip enable. In this case, all
four UARTs (A to D) are enabled when the CS pin is a
logic 0. An individual UART channel is selected by the data
contents of address bits A[3:4]. when the 16 mode is
selected (68-pin devices), this pin functions as CSA (see
denition under CSA, CSB). This pin is not available on
64-pin packages which operate in the 16 mode only.
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