參數(shù)資料
型號: ATMEGA324A-AU
廠商: Atmel
文件頁數(shù): 132/160頁
文件大?。?/td> 0K
描述: IC MCU AVR 32K 20MHZ 44TQFP
產品培訓模塊: MCU Product Line Introduction
megaAVR Introduction
標準包裝: 160
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: ATSTK600-RC31-ND - STK600 ROUTING CARD AVR
73
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
14.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 14-2. General digital I/O
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
14.2.1
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register
description” on page 91, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx:
WRITE DDRx
WRx:
WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
PUD:
PULLUP DISABLE
clk
I/O:
I/O CLOCK
RDx:
READ DDRx
D
L
Q
RESET
Q
D
Q
D
CLR
PORTxn
Q
D
CLR
DDxn
PINxn
DA
TA
B
U
S
SLEEP
SLEEP:
SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx:
WRITE PINx REGISTER
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