參數(shù)資料
| 型號： | ATF16V8BQL-15JU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD 15NS 20PLCC |
| 標準包裝： | 48 |
| 系列： | 16V8 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 8 |
| 輸入電壓： | 5V |
| 速度： | 15ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應商設備封裝： | 20-PLCC |
| 包裝： | 管件 |
| 產品目錄頁面： | 610 (CN2011-ZH PDF) |
20
7707F–AVR–11/10
AT90USB82/162
5.3.4
The EEPROM Control Register – EECR
Bits 7..6 – Res: Reserved Bits
These bits are reserved bits in the AT90USB82/162 and will always read as zero.
Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be trig-
gered when writing EEPE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 5-1. While EEPE
is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEPE is cleared.
Bit 2 – EEMPE: EEPROM Master Programming Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.
When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the
selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEPE bit for an EEPROM write procedure.
Bit 1 – EEPE: EEPROM Programming Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-
wise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1.
Wait until EEPE becomes zero.
2.
Wait until SELFPRGEN in SPMCSR becomes zero.
3.
Write new EEPROM address to EEAR (optional).
Bit
7
6
5432
10
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
EECR
Read/Write
R
R/W
Initial Value
0
X
0
X
0
Table 5-1.
EEPROM Mode Bits
EEPM1
EEPM0
Programming
Time
Operation
0
3.4 ms
Erase and Write in one operation (Atomic Operation)
0
1
1.8 ms
Erase Only
1
0
1.8 ms
Write Only
1
–
Reserved for future use
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| ATF16V8BQL-15PU | 功能描述:EEPLD - 電子擦除可編程邏輯設備 15 ns 20 I/O Pins 8 macorcells 8 reg RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數(shù)量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數(shù):8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數(shù)量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
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